ATA5428-PLSW datasheet(53/100 Pages) ATMEL

53 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

To save current it is recommended that CLK and V

VSOUT be disabled during RX polling mode. IP

does not include the current of the Microcontroller_Interface, I

VSINT, or the current of an external

device connected to pin VSOUT (for example, microcontroller). If CLK and/or VSOUT is enabled

during RX polling mode the current consumption is calculated as follows:

During T

Sleep, TStartup_PLL and TStartup_Sig_Proc, the transceiver is not sensitive to a transmitter sig-

nal. To guarantee the reception of a transmitted command, the transmitter must start the

telegram with an adequate preburst. The required length of the preburst, T

Preburst, depends on

the polling parameters T

Sleep, TStartup_PLL, TStartup_Sig_Proc and TBit-check. Thus, TBit-check depends on

the actual bit rate and the number of bits (N

Bit-check) to be tested.

9.1.2

Sleep Mode

The length of period T

Sleep is defined by the 5-bit word sleep in control register 4, the extension

factor X

Sleep defined by the bit XSleep in control register 4, and the basic clock cycle TDCLK. It is

calculated to be:

In US and European applications, the maximum value of T

Sleep is about 38 ms if XSleep is set to 1

(which is done by setting the bit X

Sleep in control register 4 to “0”). The time resolution is about

1.2 ms in that case. The sleep time can be extended to about 300 ms by setting X

Sleep to 8

(which is done by setting X

Sleep in control register 4 to “1”), the time resolution is then about

9.6 ms.

9.1.3

Start-up Mode

During T

Startup_PLL the PLL is enabled and starts up. If the PLL is locked, the signal processing

circuit starts up (T

Startup_Sig_Proc). After the start-up time all circuits are in stable condition and

ready to receive.

S_Poll

VSINT

EXT

Preburst

Sleep

Startup_PLL

Startup_Sig_Proc

Bit_check

≥

Sleep

1024

DCLK

Sleep

ATA5428-PLSW Datasheet(PDF) 53 Page - ATMEL Corporation

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