ATA5428-PLSW datasheet(55/100 Pages) ATMEL

55 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Figure 9-2.

Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)

Start RX Mode

Start RX Polling Mode

Start-up PLL:

The PLL is enabled and locked.

Output level on pin RX_ACTIVE

⇒ High; I

S = IStartup_PLL_X; IStartup_PLL

Start-up signal processing:

The signal processing circuit are enabled.

Output level on pin RX_ACTIVE

⇒ High; I

S = IRX_X; TStartup_Sig_proc

The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,

the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to

receiving mode. Otherwise the transceiver is set to Sleep mode

(if OPM0 = 0 and T

Sleep > 0) or stays in Bit-check mode.

Output level on pin RX_ACTIVE

⇒ High

Bit-check mode:

Sleep:

Defined by bits Sleep 0 to Sleep 4 in Control

798.5

× T

DCLK (typ)

Startup_PLL:

(BR_Range 0)

Is defined by the selected baud rate range and

DCLK .The baud-rate range is defined by bit

Baud 0 and Baud 1 in Control Register 6.

If the bit check is ok, T

Bit-check depends on the

number of bits to be checked (N

Bit-check) and

on the utilized data rate.

882

× T

DCLK

(BR_Range 1)

498

× T

DCLK

(BR_Range 2)

306

× T

DCLK

(BR_Range 3)

210

× T

DCLK

Startup_Sig_Proc:

Defined by bit XSleep in Control register 4

Basic clock cycle

DCLK:

Sleep:

Depends on the result of the bit check.

Bit-check:

All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.

Output level on pin RX_ACTIVE

⇒ Low; I

S = IIDLE_X

Sleep = Sleep × 1024 × TDCLK × XSleep

Sleep mode:

Start-up mode:

Bit check

OK ?

YES

Set VSOUT_EN = 1

Set CLK_ON = 1

Set OPM0 = 1

SLEEP = 0

OPM0 = 1

S = IRX_X; TBit-check

The incomming data stream is passed via PIN SDO_TMDO to the connected

microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.

Output level on pin RX_ACTIVE

⇒ High

Receiving mode:

Level on pin

CS = Low ?

YES

RX data stream

available on pin

SDO_TMDO

S = IRX_X

If the bit check fails, the average time period for

that check despends on the selected bit-rate

range and on T

XDCLK. The bit-rate range is

defined by bit Baud 0 and Baud 1 in Control

If in FSK mode the datastream is interrupted the

FSK-Demodulator-PLL tends to lock out and is

further not able to lock in, even there is a valid

data stream available.

In this case the transceiver must be set back to

IDLE mode.

ATA5428-PLSW Datasheet(PDF) 55 Page - ATMEL Corporation

ATA5428-PLSW Datasheet(HTML) 55 Page - ATMEL Corporation

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