ATA5428-PLSW datasheet(44/100 Pages) ATMEL

44 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

7.5

Pin Tn

To switch the transceiver from OFF to IDLE mode, pin Tn must be set to “0” (maximum

0.2

× V

VS2) for at least TTn_IRQ (see Figure 7-2). The transceiver recognizes the negative edge,

sets pin N_RESET to low and switches on DVCC, AVCC and the power supply for external

devices VSOUT.

If V

DVCC exceeds 1.5V (typically) and the XTO is settled, the digital control logic is active and

sets the status bit STn to “1” and an interrupt is issued (T

Tn_IRQ).

After the voltage on pin VSOUT exceeds 2.3V (typically) and the start-up time of the XTO is

elapsed, the output clock on pin CLK is available. Because the enabling of pin CLK is asynchro-

nous, the first clock cycle may be incomplete. N_RESET is set to high if V

VSOUT exceeds 2.38V

(typically) and the XTO is settled.

Figure 7-2.

Timing Pin Tn, Status Bit STn

Power_On

Indicates that the transceiver was woken up by pin PWR_ON (rising edge on pin

PWR_ON). During Power_On = 1, the bits VSOUT_EN and CLK_ON in control register 3

are set to “1”.

(see Figure 7-4 on page 46)

Low_Batt

Indicates that output voltage on pin VSOUT is too low

VSOUT < 2.38V typically)

(see Figure 7-5 on page 47)

P_On_Aux

Indicates that the auxiliary supply voltage on pin VAUX is high enough to operate.

State transition:

a) OFF mode

→ AUX mode (see Figure 5-2 on page 32)

b) IDLE mode (VSOUT = VS1)

→ IDLE mode (VSOUT = V_REG2)

(see Figure 7-6 on page 48)

Table 7-22.

Status Register (Continued)

Status Bit

Function

STn

(Status register)

IRQ

CLK

N_RESET

DVCC, AVCC

VSOUT

IDLE

Mode

OFF

Mode

Thres_2 = 2.38V (typ)

Thres_1 = 2.3V (typ)

Tn_IRQ

1.5V (typ)

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