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ATA5428-PLSW Datasheet(PDF) 41 Page - ATMEL Corporation |
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ATA5428-PLSW Datasheet(HTML) 41 Page - ATMEL Corporation |
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41 / 100 page  41 4841D–WIRE–10/07 ATA5423/ATA5425/ATA5428/ATA5429 7.3.5 Control Register 5 (ADR 4) Table 7-14. Control Register 4 (Function of Bit 6, Bit 5, Bit 4, Bit 3 and Bit 2) Sleep4 24 Sleep3 23 Sleep2 22 Sleep1 21 Sleep0 20 Function (RX Mode) Sleep (TSleep = Sleep × 1024 × TDCLK × XSleep) 00 00 0 0 00 00 1 1 . ... . 01 01 0 10 (T Sleep = 10 × 1024 × TDCLK × XSleep) (default) . ... . 11 11 1 31 Table 7-15. Control Register 4 (Function of Bit 1) XSleep Function 0XSleep = 1; extended TSleep off (default) 1XSleep = 8; extended TSleep on Table 7-16. Control Register 4 (Function of Bit 0) XLim Function 0X Lim = 1; extended TLim_min, TLim_max off (default) 1X Lim = 2; extended TLim_min, TLim_max on Table 7-17. Control Register 5 (Function of Bit 7 and Bit 6) BitChk1 BitChk0 Function 00 NBit-check = 0 (0 bits checked during bit check) 01 NBit-check = 3 (3 bits checked during bit check) (default) 10 NBit-check = 6 (6 bits checked during bit check) 11 NBit-check = 9 (9 bits checked during bit check) |
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