MMA8450QT datasheet(41/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

IPOL bit selects the polarity of the interrupt signal. When IPOL is ‘0’ any interrupt event will signalled with a logical 0.

PP_OD bit configures the interrupt pin to Push-Pull or in Open Drain mode. The open drain configuration can be used for

connecting multiple interrupt signals on the same interrupt line.

0x3C: CTRL_REG5 Register (Read/Write)

Table 58. CTRL_REG3 Description

FIFO_GATE

0: FIFO gate is bypassed. FIFO is flushed upon the system mode transitioning from wake-to-sleep mode or from sleep-to-

wake mode.

1: The FIFO input buffer is blocked when transitioning from “wake-to-sleep” mode or from “sleep-to-wake” mode until the

FIFO is flushed. Although the system transitions from “wake-to-sleep” or from “sleep-to-wake” the contents of the FIFO

buffer are preserved, new data samples are ignored until the FIFO is emptied by the host application.

If the FIFO_GATE bit is set to logic 1 and the FIFO buffer is not emptied before the arrival of the next sample, then the

FGERR bit in the SYS_MOD register (0x14) will be asserted. The FGERR bit remains asserted as long as the FIFO buffer

remains un-emptied.

Emptying the FIFO buffer clears the FGERR bit in the SYS_MOD register.

WAKE_TRANS

0: Transient function is bypassed in sleep mode

1: Transient function interrupt can wake up system

WAKE_LNDPRT

0: Orientation function is bypassed in sleep mode

1: Orientation function interrupt can wake up system

WAKE_PULSE

0: Pulse function is bypassed in sleep mode

1: Pulse function interrupt can wake up system

WAKE_FF_MT_1

0: Freefall/Motion1 function is bypassed in sleep mode

1: Freefall/Motion1 function interrupt can wake up

WAKE_FF_MT_2

0: Freefall/Motion2 function is bypassed in sleep mode

1: Freefall/Motion2 function interrupt can wake up system

IPOL

Interrupt polarity active high, or active low. Default value 0.

0: active low; 1: active high

PP_OD

Push-pull/Open Drain selection on interrupt pad. Default value 0.

0: push-pull; 1: open drain

0x3C CTRL_REG5 Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_EN_ASLP

INT_EN_FIFO

INT_EN_TRANS

INT_EN_LNDPRT

INT_EN_PULSE

INT_EN_FF_MT_1

INT_EN_FF_MT_2

INT_EN_DRDY

Table 59. interrupt Enable Register Description

Interrupt Enable

Description

INT_EN_ASLP