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MMA8450QT Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

Part # MMA8450QT
Description  3-Axis, 8-bit/12-bit Digital Accelerometer
PDF  57 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMA8450QT Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

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Sensors
Freescale Semiconductor
18
MMA8450Q
Multiple Byte Read
When performing a multi-byte read or “burst read”, the MMA8450Q automatically increments the received register address
commands after a read command is received. Therefore, after following the steps of a single byte read, multiple bytes of data
can be read from sequential registers after each MMA8450Q acknowledgment (AK) is received until a NACK is received from
the Master followed by a stop condition (SP) signaling an end of transmission.
Single Byte Write
To start a write command, the Master transmits a start condition (ST) to the MMA8450Q, slave address ($1D) with the R/W bit
set to “0” for a write, the MMA8450Q sends an acknowledgement. Then the Master (MCU) transmits the address of the register
to write to, and the MMA8450Q sends an acknowledgement. Then the Master (or MCU) transmits the 8-bit data to write to the
designated register and the MMA8450Q sends an acknowledgement that it has received the data. Since this transmission is
complete, the Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8450Q is now stored in the
appropriate register.
Multiple Byte Write
The MMA8450Q automatically increments the received register address commands after a write command is received.
Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each
MMA8450Q acknowledgment (ACK) is received.
Figure 11. I2C Timing Diagram
Table 10. I2C device Address Sequence
Command
[6:1]
Device Address
[0]
SA0
[6:0]
Device Address
R/W
8-bit Final Value
Read
001110
0
0x1C
1
0x39
Write
001110
0
0x1C
0
0x38
Read
001110
1
0x1D
1
0x3B
Write
001110
1
0x1D
0
0x3A
< Single Byte Read >
Master
ST
Device Address [6:0]
W
Register Address [7:0]
SR Device Address [6:0]
R
NAK SP
Slave
AK
AK
AK
Data [7:0]
< Multiple Byte Read >
Master
ST
Device Address [6:0]
W
Register Address [7:0]
SR Device Address [6:0]
R
AK
Slave
AK
AK
AK
Data [7:0]
Master
AK
AK
NAK
SP
Slave
Data [7:0]
Data [7:0]
Data [7:0]
< Single Byte Write >
Master
ST
Device Address [6:0]
W
Register Address [7:0]
Data [7:0]
SP
Slave
AK
AK
AK
< Multiple Byte Write >
Master
ST
Device Address [6:0]
W
Register Address [7:0]
Data [7:0]
Data [7:0]
Slave
AK
AK
AK
AK
Legend
ST: Start Condition
SP: Stop Condition
NAK: No Acknowledge
W: Write = 0
SR: Repeated Start Condition
AK: Acknowledge
R: Read = 1



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