MMA8450QT datasheet(20/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

Note: Auto-increment addresses which are not a simple increment are highlighted in bold. The auto-increment addressing is only enabled when

device registers are read using I2C burst read mode. Therefore the internal storage of the auto-increment address is clear whenever a

stop-bit is detected.

PL_P_L_THS_REG2(1)(4)

R/W

0x1E

0x1F

00100010

Portrait-to-Landscape Trip Angle is 30°

PL_P_L_THS_REG3(1)(4)

R/W

0x1F

0x20

11010100

Portrait-to-Landscape Trip Angle is 30°

PL_L_P_THS_REG1(1)(4)

R/W

0x20

0x21

00101101

Landscape-to-Portrait Trip Angle is 60°

PL_L_P_THS_REG2(1)(4)

R/W

0x21

0x22

01000001

Landscape-to-Portrait Trip Angle is 60°

PL_L_P_THS_REG3(1)(4)

R/W

0x22

0x23

10100010

Landscape-to-Portrait Trip Angle is 60°

FF_MT_CFG_1(1)(4)

R/W

0x23

0x24

00000000

Freefall/Motion1 configuration

FF_MT_SRC_1(1)(2)

0x24

0x25

00000000

Freefall/Motion1 event source register

FF_MT_THS_1(1)(3)

R/W

0x25

0x26

00000000

Freefall/Motion1 threshold register

FF_MT_COUNT_1(1)(3)

R/W

0x26

0x27

00000000

Freefall/Motion1 debounce counter

FF_MT_CFG_2(1)(4)

R/W

0x27

0x28

00000000

Freefall/Motion2 configuration

FF_MT_SRC_2(1)(2)

0x28

0x29

00000000

Freefall/Motion2 event source register

FF_MT_THS_2(1)(3)

R/W

0x29

0x2A

00000000

Freefall/Motion2 threshold register

FF_MT_COUNT_2(1)(3)

R/W

0x2A

0x2B

00000000

Freefall/Motion2 debounce counter

TRANSIENT_CFG(1)(4)

R/W

0x2B

0x2C

00000000

Transient configuration

TRANSIENT_SRC(1)(2)

0x2C

0x2D

00000000

Transient event status register

TRANSIENT_THS(1)(3)

R/W

0x2D

0x2E

00000000

Transient event threshold

TRANSIENT_COUNT(1)(3)

R/W

0x2E

0x2F

00000000

Transient debounce counter

PULSE_CFG(1)(4)

R/W

0x2F

0x30

00000000

ELE, Double_XYZ or Single_XYZ

PULSE_SRC(1)(2)

0x30

0x31

00000000

EA, Double_XYZ or Single_XYZ

PULSE_THSX(1)(3)

R/W

0x31

0x32

00000000

X and Y pulse threshold

PULSE_THSY(1)(3)

R/W

0x32

0x33

00000000

Z pulse threshold

PULSE_THSZ(1)(3)

R/W

0x33

0x34

00000000

Z pulse threshold

PULSE_TMLT(1)(4)

R/W

0x34

0x35

00000000

Time limit for pulse

PULSE_LTCY(1)(4)

R/W

0x35

0x36

00000000

Latency time for 2nd pulse

PULSE_WIND(1)(4)

R/W

0x36

0x37

00000000

Window time for 2nd pulse

ASLP_COUNT(1)(4)

R/W

0x37

0x38

00000000

Counter setting for auto-sleep

CTRL_REG1(1)(4)

R/W

0x38

0x39

00000000

ODR = 400Hz, Standby Mode.

CTRL_REG2(1)(4)

R/W

0x39

0x3A

00000000

ST = Disabled, SLPE = Disabled,

MODS = normal mode.

CTRL_REG3(1)(4)

R/W

0x3A

0x3B

00000000

IPOL, PP_OD

CTRL_REG4(1)(4)

R/W

0x3B

0x3C

00000000

Interrupt enable register

CTRL_REG5(1)(4)

R/W

0x3C

0x3D

00000000

Interrupt pin (INT1/INT2) map configuration

OFF_X(1)(4)

R/W

0x3D

0x3E

00000000

X-axis offset adjust

OFF_Y(1)(4)

R/W

0x3E

0x3F

00000000

Y-axis offset adjust

OFF_Z(1)(4)

R/W

0x3F

0x0F

00000000

Z-axis offset adjust

1. Register contents are preserved when transition from “ACTIVE” to “STANDBY” mode occurs.

2. Register contents are reset when transition from “STANDBY” to “ACTIVE” mode occurs.

3. Modification of this register’s contents can only occur when device is “STANDBY” mode

4. Register contents can be modified anytime in “STANDBY” or “ACTIVE” mode. A write to this register will cause a reset of the corresponding

internal system debounce counter.

Table 11. Register Address Map

MMA8450QT Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc

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