MMA8450QT datasheet(17/57 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA8450Q

5.10

Serial I2C Interface

Acceleration data may be accessed through an I2C interface thus making the device particularly suitable for direct interfacing

with a microcontroller. The MMA8450Q features an interrupt signal which indicates when a new set of measured acceleration

data is available thus simplifying data synchronization in the digital system that uses the device. The MMA8450Q may also be

configured to generate other interrupt signals accordingly to the programmable embedded functions of the device for Motion,

Freefall, Transient, Orientation, and Tap.

The registers embedded inside MMA8450Q are accessed through an I2C serial interface. To enable the I2C interface, the EN

pin (pin 8) must be tied high. When EN is tied low, MMA8450Q is put into low power shutdown mode and communications on the

I2C interface are ignored. The MMA8450Q is always in slave mode. The I2C interface may be used for communications between

other I2C devices when EN is tied low and the MMA8450Q does not clamp the I2C bus.

There are two signals associated with the I2C bus; the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a

bidirectional line used for sending and receiving the data to/from the interface. External 4.7 k

Ω pull-up resistors connected to

VDD are expected for SDA and SCL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode

(400 kHz), and normal mode (100 kHz) I2C standards (Table 4).

5.10.1

I2C Operation

The transaction on the bus is started through a start condition (START) signal. START condition is defined as a HIGH to LOW

transition on the data line while the SCL line is held HIGH. After START has been transmitted by the Master, the bus is considered

busy. The next byte of data transmitted after START contains the slave address in the first 7 bits, and the eighth bit tells whether

the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system

compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the

Master. The 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The

transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it remains

stable low during the high period of the acknowledge clock period.

The number of bytes transferred per transfer is unlimited. If a receiver can't receive another complete byte of data until it has

performed some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only

continues when the receiver is ready for another byte and releases the data line. This delay action is called clock stretching.

A LOW to HIGH transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer is

always terminated by a STOP. A Master may also issue a repeated START during a data transfer. The MMA8450Q expects

repeated STARTs to be used to randomly read from specific registers.

The MMA8450Q's standard slave address is a choice between the two sequential addresses 0011100 and 0011101. The

selection is made by the high and low logic level of the SA0 (pin 7) input respectively. The slave addresses are factory

programmed and alternate addresses are available at customer request. The format is shown in Table 9.

Single Byte Read

The MMA8450Q has an internal ADC that can sample, convert and return sensor data on request. The transmission of an 8-

bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that the data

returned is sent with the MSB first once the data is received. Figure 11 shows the timing diagram for the accelerometer 8-bit I2C

read operation. The Master (or MCU) transmits a start condition (ST) to the MMA8450Q, slave address ($1D), with the R/W bit

set to “0” for a write, and the MMA8450Q sends an acknowledgement. Then the Master (or MCU) transmits the address of the

register to read and the MMA8450Q sends an acknowledgement. The Master (or MCU) transmits a repeated start condition (SR)

and then addresses the MMA8450Q ($1D) with the R/W bit set to “1” for a read from the previously selected register. The Slave

then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NAK) it received the

transmitted data, but transmits a stop condition to end the data transfer.

Table 8. Serial Interface Pin Description

Pin Name

Pin Description

Device enable

(1: I2C mode enabled; 0: Shutdown mode)

SCL

I2C Serial Clock

SDA

I2C Serial Data

SA0

I2C least significant bit of the device address

Table 9. I2C Address Selection Table

Slave Address (SA0 = 0)

Slave Address (SA0 = 1)

Comment

0011100

0011101

Factory Default

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