SPMCK16Z4MPV16 datasheet(267/500 Pages) FREESCALE

267 / 500 page

M68HC16 Z SERIES

GENERAL-PURPOSE TIMER

USER’S MANUAL

11-3

Refer to D.8 General-Purpose Timer for a GPT address map and register bit/field de-

scriptions. Refer to 5.2.1 Module Mapping for more information about how the state

of MM affects the system.

11.3 Special Modes of Operation

The GPT module configuration register (GPTMCR) is used to control special GPT op-

erating modes. These include low-power stop mode, freeze mode, single-step mode,

and test mode. Normal GPT operation can be polled or interrupt-driven. Refer to 11.4

Polled and Interrupt-Driven Operation for more information.

11.3.1 Low-Power Stop Mode

Low-power stop operation is initiated by setting the STOP bit in GPTMCR. In stop

mode the system clock to the module is turned off. The clock remains off until STOP

is negated or a reset occurs. All counters and prescalers within the timer stop counting

while the STOP bit is set. Only the module configuration register (GPTMCR) and the

interrupt configuration register (ICR) should be accessed while in the stop mode. Ac-

cesses to other GPT registers cause unpredictable behavior. Low-power stop can also

be used to disable module operation during debugging.

11.3.2 Freeze Mode

The freeze (FRZ[1:0]) bits in GPTMCR are used to determine what action is taken by

the GPT when the IMB FREEZE signal is asserted. FREEZE is asserted when the

CPU enters background debug mode. At the present time, FRZ1 is not implemented;

FRZ0 causes the GPT to enter freeze mode. Refer to 4.14.4 Background Debug

Mode for more information.

Freeze mode freezes the current state of the timer. The prescaler and the pulse accu-

mulator do not increment and changes to the pins are ignored (input pin synchronizers

are not clocked). All of the other timer functions that are controlled by the CPU operate

normally. For example, registers can be written to change pin directions, force output

compares, and read or write I/O pins.

While the FREEZE signal is asserted, the CPU has write access to registers and bits

that are normally read-only or write-once. The write-once bits can be written to as often

as needed. The prescaler and the pulse accumulator remain stopped and the input

pins are ignored until the FREEZE signal is negated (the CPU is no longer in BDM),

the FRZ0 bit is cleared, or the MCU is reset.

Activities that are in progress before FREEZE assertion are completed. For example,

if an input edge on an input capture pin is detected just as the FREEZE signal is as-

serted, the capture occurs and the corresponding interrupt flag is set.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMCK16Z4MPV16 Datasheet(PDF) 267 Page - Freescale Semiconductor, Inc

SPMCK16Z4MPV16 Datasheet(HTML) 267 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL