SPMCK16Z4MPV16 datasheet(67/500 Pages) FREESCALE

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M68HC16 Z SERIES

CENTRAL PROCESSOR UNIT

USER’S MANUAL

4-7

Signed 36-bit fixed-point numbers are used only by the MAC unit. Bit 35 is the sign bit.

Bits [34:31] are sign extension bits. There is an implied radix point between bits 31 and

30. There are 31 bits of magnitude, but use of the extension bits allows representation

of numbers in the range –16 ($800000000) to 15.999969482 ($7FFFFFFFF).

4.5 Memory Organization

Both program and data memory are divided into sixteen 64-Kbyte banks. Addressing

is linear. A 20-bit extended address can access any byte location in the appropriate

address space.

A word is composed of two consecutive bytes. A word address is normally an even

byte address. Byte 0 of a word has a lower 16-bit address than byte 1. Long words and

32-bit signed fractions consist of two consecutive words, and are normally accessed

at the address of byte 0 in word 0.

Instruction fetches always access word addresses. Word operands are normally ac-

cessed at even byte addresses, but can be accessed at odd byte addresses, with a

substantial performance penalty.

To permit compatibility with the M68HC11, misaligned word transfers and misaligned

stack accesses are allowed. Transferring a misaligned word requires two successive

byte transfer operations.

Figure 4-3 shows how each CPU16 data type is organized in memory. Consecutive

even addresses show size and alignment.

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SPMCK16Z4MPV16 Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc