SPMCK16Z4MPV16 datasheet(100/500 Pages) FREESCALE

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CENTRAL PROCESSING UNIT

M68HC16 Z SERIES

4-40

USER’S MANUAL

4.13.5 Multiple Exceptions

Each exception has a hardware priority based upon its relative importance to system

operation. Asynchronous exceptions have higher priorities than synchronous excep-

tions. Exception processing for multiple exceptions is completed by priority, from high-

est to lowest. Priority governs the order in which exception processing occurs, not the

order in which exception handlers are executed.

Unless a bus error, a breakpoint, or a reset occurs during exception processing, the

first instruction of all exception handler routines is guaranteed to execute before an-

other exception is processed. Because interrupt exceptions have higher priority than

synchronous exceptions, the first instruction in an interrupt handler is executed before

other interrupts are sensed.

Bus error, breakpoint, and reset exceptions that occur during exception processing of

a previous exception are processed before the first instruction of that exception’s han-

dler routine. The converse is not true. If an interrupt occurs during bus error exception

processing, for example, the first instruction of the exception handler is executed be-

fore interrupts are sensed. This permits the exception handler to mask interrupts dur-

ing execution.

Refer to SECTION 5 SYSTEM INTEGRATION MODULE for detailed information con-

cerning interrupts and system reset. For information concerning processing of specific

exceptions, refer to the

CPU16 Reference Manual (CPU16RM/AD).

4.13.6 RTI Instruction

The return-from-interrupt instruction (RTI) must be the last instruction in all exception

handlers except the RESET handler. RTI pulls the exception stack frame that was

pushed onto the system stack during exception processing, and restores processor

state. Normal program flow resumes at the address of the instruction that follows the

last instruction executed before exception processing began.

RTI is not used in the RESET handler because RESET initializes the stack pointer and

does not create a stack frame.

4.14 Development Support

The CPU16 incorporates powerful tools for tracking program execution and for system

debugging. These tools are deterministic opcode tracking, breakpoint exceptions, and

background debug mode. Judicious use of CPU16 capabilities permits in-circuit emu-

lation and system debugging using a bus state analyzer, a simple serial interface, and

a terminal.

4.14.1 Deterministic Opcode Tracking

The CPU16 has two multiplexed outputs, IPIPE0 and IPIPE1, that enable external

hardware to monitor the instruction pipeline during normal program execution. The sig-

nals IPIPE0 and IPIPE1 can be demultiplexed into six pipeline state signals that allow

a state analyzer to synchronize with instruction stream activity.

Freescale Semiconductor, Inc.

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