SPMCK16Z4MPV16 datasheet(93/500 Pages) FREESCALE

93 / 500 page

M68HC16 Z SERIES

CENTRAL PROCESSING UNIT

USER’S MANUAL

4-33

4.9 Instruction Format

CPU16 instructions consist of an 8-bit opcode that can be preceded by an 8-bit prebyte

and followed by one or more operands.

Opcodes are mapped in four 256-instruction pages. Page 0 opcodes stand alone.

Page 1, 2, and 3 opcodes are pointed to by a prebyte code on page 0. The prebytes

are $17 (page 1), $27 (page 2), and $37 (page 3).

Operands can be four bits, eight bits or sixteen bits in length. Since the CPU16 fetches

16-bit instruction words from even-byte boundaries, each instruction must contain an

even number of bytes.

Operands are organized as bytes, words, or a combination of bytes and words. Oper-

ands of four bits are either zero-extended to eight bits, or packed two to a byte. The

largest instructions are six bytes in length. Size, order, and function of operands are

evaluated when an instruction is decoded.

A page 0 opcode and an 8-bit operand can be fetched simultaneously. Instructions

that use 8-bit indexed, immediate, and relative addressing modes have this form.

Code written with these instructions is very compact.

Figure 4-4 shows basic CPU16 instruction formats.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMCK16Z4MPV16 Datasheet(PDF) 93 Page - Freescale Semiconductor, Inc