SPMCK16Z4MPV16 datasheet(7/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

(Continued)

Paragraph

Title

Page

TABLE OF CONTENTS

5.8.1

Interrupt Exception Processing .......................................................5-58

5.8.2

Interrupt Priority and Recognition ....................................................5-58

5.8.3

Interrupt Acknowledge and Arbitration ............................................5-59

5.8.4

Interrupt Processing Summary ........................................................5-60

5.8.5

Interrupt Acknowledge Bus Cycles ..................................................5-61

5.9

Chip-Selects ............................................................................................5-61

5.9.1

Chip-Select Registers ......................................................................5-63

5.9.1.1

Chip-Select Pin Assignment Registers ...................................5-64

5.9.1.2

Chip-Select Base Address Registers ......................................5-65

5.9.1.3

Chip-Select Option Registers ..................................................5-66

5.9.1.4

PORTC Data Register .............................................................5-67

5.9.2

Chip-Select Operation .....................................................................5-67

5.9.3

Using Chip-Select Signals for Interrupt Acknowledge .....................5-68

5.9.4

Chip-Select Reset Operation ...........................................................5-69

5.10

Parallel Input/Output Ports ......................................................................5-70

5.10.1

Pin Assignment Registers ...............................................................5-70

5.10.2

Data Direction Registers .................................................................5-70

5.10.3

Data Registers .................................................................................5-71

5.11

Factory Test ............................................................................................5-71

SECTION 6

STANDBY RAM MODULE

6.1

SRAM Register Block ................................................................................6-1

6.2

SRAM Array Address Mapping .................................................................6-2

6.3

SRAM Array Address Space Type ............................................................6-2

6.4

Normal Access ..........................................................................................6-2

6.5

Standby and Low-Power Stop Operation ..................................................6-2

6.6

Reset .........................................................................................................6-3

SECTION 7

MASKED ROM MODULE

7.1

MRM Register Block ..................................................................................7-1

7.2

MRM Array Address Mapping ...................................................................7-1

7.3

MRM Array Address Space Type ..............................................................7-2

7.4

Normal Access ..........................................................................................7-2

7.5

Low-Power Stop Mode Operation .............................................................7-3

7.6

ROM Signature ..........................................................................................7-3

7.7

Reset .........................................................................................................7-3

Freescale Semiconductor, Inc.

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