SPMCK16Z4MPV16 datasheet(96/500 Pages) FREESCALE

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CENTRAL PROCESSING UNIT

M68HC16 Z SERIES

4-36

USER’S MANUAL

4.11 Execution Process

Fetched opcodes are latched into stage A, then advanced to stage B. Opcodes are

evaluated in stage B. The execution unit can access operands in either stage A or

stage B (stage B accesses are limited to 8-bit operands). When execution is complete,

opcodes are moved from stage B to stage C, where they remain until the next instruc-

tion is complete.

A prefetch mechanism in the microsequencer reads instruction words from memory

and increments the program counter. When instruction execution begins, the program

counter points to an address six bytes after the address of the first word of the instruc-

tion being executed.

The number of machine cycles necessary to complete an execution sequence varies

according to the complexity of the instruction. Refer to the

CPU16 Reference Manual

(CPU16RM/AD) for details.

4.11.1 Changes in Program Flow

When program flow changes, instructions are fetched from a new address. Before ex-

ecution can begin at the new address, instructions and operands from the previous in-

struction stream must be removed from the pipeline. If a change in flow is temporary,

a return address must be stored, so that execution of the original instruction stream

can resume after the change in flow.

When an instruction that causes a change in program flow executes, PK : PC point to

the address of the first word of the instruction + $0006. During execution of the instruc-

tion, PK : PC is loaded with the address of the first instruction word in the new instruc-

tion stream. However, stages A and B still contain words from the old instruction

stream. Extra processing steps must be performed before execution from the new in-

struction stream.

4.12 Instruction Timing

The execution time of CPU16 instructions has three components:

• Bus cycles required to prefetch the next instruction

• Bus cycles required for operand accesses

• Time required for internal operations

A bus cycle requires a minimum of two system clock periods. If the access time of a

memory device is greater than two clock periods, bus cycles are longer. However, all

bus cycles must be an integer number of clock periods. CPU16 internal operations are

always an integer multiple of two clock periods.

Dynamic bus sizing affects bus cycle time. The integration module manages all ac-

cesses. Refer to SECTION 5 SYSTEM INTEGRATION MODULE for more informa-

tion.

The CPU16 does not execute more than one instruction at a time. The total time re-

quired to execute a particular instruction stream can be calculated by summing the in-

dividual execution times of each instruction in the stream.

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SPMCK16Z4MPV16 Datasheet(PDF) 96 Page - Freescale Semiconductor, Inc

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