SPMCK16Z4MPV16 datasheet(102/500 Pages) FREESCALE

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CENTRAL PROCESSING UNIT

M68HC16 Z SERIES

4-42

USER’S MANUAL

Breakpoints on instructions that are flushed from the pipeline before execution are not

acknowledged. Operand breakpoints are always acknowledged. There is no break-

point acknowledge bus cycle when BDM is entered. Refer to 5.6.4.1 Breakpoint Ac-

knowledge Cycle for more information about breakpoints.

4.14.3 Opcode Tracking and Breakpoints

Breakpoints are acknowledged after a tagged instruction has executed, that is, when

the instruction is copied from pipeline stage B to stage C. Stage C contains the opcode

of the previous instruction when execution of the current instruction begins.

When an instruction is tagged, IPIPE0/IPIPE1 reflect the start of execution and the ap-

propriate number of pipeline advances and operand fetches before the breakpoint is

acknowledged. If background debug mode is enabled, these signals model the pipe-

line before BDM is entered.

4.14.4 Background Debug Mode

Microprocessor debugging programs are generally implemented in external software.

CPU16 BDM provides a debugger implemented in CPU microcode. BDM incorporates

a full set of debug options. Registers can be viewed and altered, memory can be read

or written, and test features can be invoked. BDM is an alternate CPU16 operating

mode. While the CPU16 is in BDM, normal instruction execution is suspended, and

special microcode performs debugging functions under external control. While in

BDM, the CPU16 ceases to fetch instructions through the data bus and communicates

with the development system through a dedicated serial interface.

4.14.4.1 Enabling BDM

The CPU16 samples the BKPT input during reset to determine whether to enable

BDM. When BKPT is asserted at the rising edge of the RESET signal, BDM operation

is enabled. BDM remains enabled until the next system reset. If BKPT is at logic level

one on the trailing edge of RESET, BDM is disabled. BKPT is relatched on each rising

transition of RESET. BKPT is synchronized internally and must be asserted for at least

two clock cycles before negation of RESET.

4.14.4.2 BDM Sources

When BDM is enabled, external breakpoint hardware and the BGND instruction can

cause the CPU16 to enter BDM. If BDM is not enabled when a breakpoint occurs, a

breakpoint exception is processed.

4.14.4.3 Entering BDM

When the CPU16 detects a breakpoint or decodes a BGND instruction when BDM is

enabled, it suspends instruction execution and asserts the FREEZE signal. Once

FREEZE has been asserted, the CPU16 enables the BDM serial communication hard-

ware and awaits a command. Assertion of FREEZE causes opcode tracking signals

IPIPE0 and IPIPE1 to change definition and become serial communication signals

DSO and DSI. FREEZE is asserted at the next instruction boundary after the assertion

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SPMCK16Z4MPV16 Datasheet(PDF) 102 Page - Freescale Semiconductor, Inc

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