SPMCK16Z4MPV16 datasheet(277/500 Pages) FREESCALE

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M68HC16 Z SERIES

GENERAL-PURPOSE TIMER

USER’S MANUAL

11-13

Figure 11-4 Input Capture Timing Example

An input capture occurs every time a selected edge is detected, even when the input

capture status flag is set. This means that the value read from the input capture regis-

ter corresponds to the most recent edge detected, which may not be the edge that

caused the status flag to be set.

11.8.3 Output Compare Functions

Each GPT output compare pin has an associated 16-bit compare register and a 16-bit

comparator. Each output compare function has an associated status flag, and can

cause the GPT to make an interrupt service request. Output compare logic is designed

to prevent false compares during data transition times.

When the programmed content of an output compare register matches the value in

TCNT, an output compare status flag (OCxF) bit in TFLG1 is set. If the appropriate in-

terrupt enable bit (OCxI) in TMSK1 is set, an interrupt request is made when a match

occurs. Refer to 11.4.2 GPT Interrupts for more information.

Operation of output compare 1 differs from that of the other output compare functions.

OC1 control logic can be programmed to make state changes on other OC pins when

an OC1 match occurs. Control bits in the timer compare force register (CFORC) allow

for early forced compares.

16/32 IC TIM

CAPTURE/COMPARE

CLOCK

CAPTURE REGISTER

$0102

SYNCHRONIZER

OUTPUT

ICxF FLAG

EXTERNAL PIN

TCNT

$0102

$0101

(PHI1)1

clock

PHI1 IS THE SAME FREQUENCY AS THE SYSTEM CLOCK; HOWEVER, IT DOES NOT HAVE THE SAME TIMING.

NOTES:

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV16 Datasheet(PDF) 277 Page - Freescale Semiconductor, Inc