SPMCK16Z4MPV16 datasheet(330/500 Pages) FREESCALE

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ELECTRICAL CHARACTERISTICS

M68HC16 Z SERIES

A-46

USER’S MANUAL

Table A-28 QSPI Timing

and V

DDSYN

= 5.0 Vdc

± 5% for 16.78 MHz, 10% for 20/25 MHz, V

= 0 Vdc, T

= T

to T

NOTES:

1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted.

Num

Function

Symbol

Min

Max

Unit

Operating Frequency

Master

Slave

fop

1/4

fsys

Cycle Time

Master

Slave

tqcyc

510

—

tcyc

Enable Lead Time

Master

Slave

tlead

128

—

tcyc

Enable Lag Time

Master

Slave

tlag

—

1/2

—

SCK

tcyc

Clock (SCK) High or Low Time

Master

Slave2

2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.

tsw

2 tcyc – 60

2 tcyc – n

255 tcyc

—

Sequential Transfer Delay

Master

Slave (Does Not Require Deselect)

ttd

8192

—

tcyc

Data Setup Time (Inputs)

Master

Slave

tsu

—

Data Hold Time (Inputs)

Master

Slave

thi

—

Slave Access Time

—1

tcyc

Slave MISO Disable Time

tdis

—2

tcyc

Data Valid (after SCK Edge)

Master

Slave

—

Data Hold Time (Outputs)

Master

Slave

tho

—

Rise Time

Input

Output

tri

tro

—

µs

Fall Time

Input

Output

tfi

tfo

—

µs

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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