SPMCK16Z4MPV16 datasheet(156/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-50

USER’S MANUAL

5.7.3.1 Data Bus Mode Selection

All data lines have weak internal pull-up devices. When pins are held high by the in-

ternal pull-ups, the MCU uses a default operating configuration. However, specific

lines can be held low externally during reset to achieve an alternate configuration.

NOTE

External bus loading can overcome the weak internal pull-up drivers

on data bus lines and hold pins low during reset.

Use an active device to hold data bus lines low. Data bus configuration logic must re-

lease the bus before the first bus cycle after reset to prevent conflict with external

memory devices. The first bus cycle occurs ten CLKOUT cycles after RESET is re-

leased. If external mode selection logic causes a conflict of this type, an isolation re-

sistor on the driven lines may be required. Figure 5-18 shows a recommended

method for conditioning the mode select signals.

Figure 5-18 Preferred Circuit for Data Bus Mode Select Conditioning

RESET

R/W

VDD

IN8

OUT8

TIE INPUTS

HIGH OR LOW

AS NEEDED

TIE INPUTS

HIGH OR LOW

AS NEEDED

DATA0

DATA7

DATA8

DATA15

10 k

Ω

10 k

Ω

820

Ω

OUT1

IN1

74HC244

IN8

OUT8

OUT1

IN1

74HC244

DATA BUS SELECT CONDITIONING

Freescale Semiconductor, Inc.

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