KM416RD8AS-RBM80 datasheet(43/64 Pages) SAMSUNG

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Page 40

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

PDEV5..0 address packet and exits NAP or PDN when the

wake-up sequence is presented on the CMD wire. The ROW

and COL pins must be quiet at a time tS4/tH4 around the indi-

cated falling SCK edge (timed with the PDNX or NAPX

directed to the RDRAM which is now in ATTN or STBY

state.

Figure 49 shows the constraints for entering and exiting

NAP and PDN states. On the left side, an RDRAM exits

NAP state at the end of cycle T3. This RDRAM may not re-

enter NAP or PDN state for an interval of tNU0. The

RDRAM enters NAP state at the end of cycle T13. This

RDRAM may not re-exit NAP state for an interval of tNU1.

The equations for these two parameters depend upon a

number of factors, and are shown at the bottom of the figure.

NAPX is the value in the NAPX field in the NAPX register.

On the right side of Figure 48, an RDRAM exits PDN state

at the end of cycle T3. This RDRAM may not re-enter PDN

or NAP state for an interval of tPU0. The RDRAM enters

PDN state at the end of cycle T13. This RDRAM may not re-

exit PDN state for an interval of tPU1. The equations for

these two parameters depend upon a number of factors, and

are shown at the bottom of the figure. PDNX is the value in

the PDNX field in the PDNX register.

Figure 46: STBY Entry (left) and STBY Exit (right)

STBY

ATTN

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

tAS

RLXR

Power

State

ATTN

Power

State

STBY

tSA

ROP a0

RLXC

RLXX

TFRM•t CYCLE

ROP = non-broadcast ROWA

or ROWR/ATTN

a0 = {d0,b0,r0}

a1 = {d1,b1,c1}

No COL packets may be

placed in the three

indicated positions; i.e. at

(TFRM - {1,2,3})•t CYCLE.

A COL packet to device d0

(or any other device) is okay

(TFRM)•t CYCLE

or later.

A COL packet to another

device (d1!= d0) is okay at

(TFRM - 4)•t CYCLE

or earlier.

COP a1

XOP a1

COP a1

XOP a1

COP a1

XOP a1

COP a0

XOP a0

COP a1

XOP a1

Figure 47: NAP Entry (left) and PDN Entry (right)

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

ROP a0

(NAPR)

Power

State

Power

State

a The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry

tCD

ROP a1

COP a0

XOP a0

COP a1

XOP a1

tASN

ATTN/STBYa

NAP

ROP a0

(PDNR)

ROP a1

COP a0

XOP a0

COP a1

XOP a1

tASP

ATTN/STBYa

PDN

quiet

tCD

tNPQ

restricted

a0 = {d0,b0,r0,c0}

a1 = {d1,b1,r1,c1}

No ROW or COL packets

directed to device d0 may

overlap the restricted

interval. No broadcast ROW

packets may overlap the quiet

interval.

ROW or COL packets to a

device other than d0 may

overlap the restricted

interval.

ROW or COL packets

directed to device d0 after the

restricted interval will be

ignored.

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