KM416RD8AS-RBM80 datasheet(60/64 Pages) SAMSUNG

60 / 64 page

Page 57

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

This circuit does not include pin coupling effects that are

often present in the packaged device. Because coupling

effects make the effective single-pin inductance LI, and

capacitance CI, a function of neighboring pins, these param-

eters are intrinsically data-dependent. For purposes of speci-

fying the device electrical loading on the Channel, the

effective LI and CI are defined as the worst-case values over

all specified operating conditions.

LI is defined as the effective pin inductance based on the

device pin assignment. Because the pad assignment places

each RSL signal adjacent to an AC ground (a Gnd or Vdd

pin), the effective inductance must be defined based on this

configuration. Therefore, LI assumes a loop with the RSL

pin adjacent to an AC ground.

CI is defined as the effective pin capacitance based on the

device pin assignment. It is the sum of the effective package

pin capacitance and the IO pad capacitance.

Table 25: RSL Pin Parasitics

Symbol

Parameter and Conditions - RSL pins

Min

Max

Unit

RSL effective input inductance

4.5

L12

Mutual inductance between any DQA or DQB RSL signals.

0.2

Mutual inductance between any ROW or COL RSL signals.

0.6

∆L

Difference in LI value between average of CTM/CFM and any

RSL pins of a single device.

2.0

RSL effective input capacitancea

2.0

2.6

C12

Mutual capacitance between any RSL signals.

0.1

∆C

Difference in CI value between average of CTM/CFM and any

RSL pins of a single device.

0.12

RSL effective input resistance

Ω

a. This value is a combination of the device IO circuitry and package capacitances.

Table 26: CMOS Pin Parasitics

Symbol

Parameter and Conditions - CMOS pins

Min

Max

Unit

LI ,CMOS

CMOS effective input inductance

8.0

CI ,CMOS

CMOS effective input capacitance (SCK,CMD)a

1.7

2.1

CI ,CMOS,SIO

CMOS effective input capacitance (SIO1, SIO0)

7.0

a. This value is a combination of the device IO circuitry and package capacitances.

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