KM416RD8AS-RBM80 datasheet(52/64 Pages) SAMSUNG

Part #	KM416RD8AS-RBM80

Description	128Mbit RDRAM 256K x 16 bit x 2*16 Dependent Banks Direct RDRAMTM for Consumer Package

PDF	64 Pages

Scroll/Zoom	100%

Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

Logo

52 / 64 page

Page 49

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

RSL - Transmit Timing

Figure 55 is a timing diagram which shows the detailed

requirements for the RSL output signals on the Channel.

The DQA and DQB signals are outputs to transmit informa-

tion that is received by a Direct RAC on the Channel. Each

signal is driven twice per tCYCLE interval. The beginning

and end of the even transmit window is at the 75% point of

the previous cycle and at the 25% point of the current cycle.

The beginning and end of the odd transmit window is at the

25% point and at the 75% point of the current cycle. These

transmit points are measured relative to the crossing points

of the falling CTM clock edge. The size of the actual

transmit window is less than the ideal tCYCLE/2, as indicated

by the non-zero values of tQ,MIN and tQ,MAX. The tQ param-

eters are measured at the VREF voltage point of the output

transition.

The tQR and tQF rise- and fall-time parameters are measured

at the 20% and 80% points of the output transition.

Figure 55: RSL Timing - Data Signals for Transmit

tQ,MIN

tQ,MAX

tQ,MIN

0.25•t CYCLE

VQH

50%

VQL

80%

20%

VCIH

50%

VCIL

80%

20%

CTM

CTMN

tQF

tQR

even

odd

0.75•t CYCLE

DQA

DQB

VCM

VX+

VX-

KM416RD8AS-RBM80 Datasheet(PDF) 52 Page - Samsung semiconductor

KM416RD8AS-RBM80 Datasheet(HTML) 52 Page - Samsung semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL