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KM416RD8AS-RBM80 Datasheet(PDF) 47 Page - Samsung semiconductor |
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KM416RD8AS-RBM80 Datasheet(HTML) 47 Page - Samsung semiconductor |
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47 / 64 page ![]() Page 44 KM416RD8AS Direct RDRAM™ Rev. 0.9July 1999 Target Electrical Conditions Timing Conditions Table 18: Electrical Conditions Symbol Parameter and Conditions Min Max Unit TJ Junction temperature under bias 0 90 °C VDD, VDDA Supply voltage 2.50 2.50 + 0.2 V VDD,N, VDDA,N Supply voltage droop (DC) during NAP interval (tNLIMIT) - 2.0 % vDD,N, vDDA,N Supply voltage ripple (AC) during NAP interval (tNLIMIT) -2.0 2.0 % VCMOS Supply voltage for CMOS pins (2.5V controllers) 2.50 2.50 + 0.25 V Supply voltage for CMOS pins (1.8V controllers) 1.80 1.80 + 0.2 V VTERM Termination voltage 2.0 - 0.1 2.0 + 0.1 V VREF Reference voltage 1.6 - 0.12 1.6 + 0.12 V VDIL RSL data input - low voltage VREF - 0.5 VREF - 0.3 V VDIH RSL data input - high voltage VREF + 0.3 VREF + 0.5 V VDIS RSL data input swing: VDIS = VDIH - VDIL 0.6 1.0 V ADI RSL data asymmetry: ADI = [(VDIH - VREF) + (VDIL - VREF)]/VDIS -5 5 % VX RSL clock input - crossing point of true and complement signals 1.5 2.0 V VCM RSL clock input - common mode VCM = (VCIH+VCIL)/2 1.6 1.9 V VCIS,CTM RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins). 0.6 0.70 V VCIS,CFM RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins). 0.6 0.70 V VIL,CMOS CMOS input low voltage - 0.3 VCMOS/2 - 0.25 V VIH,CMOS CMOS input high voltage VCMOS/2 + 0.25 VCMOS+0.3 V Table 19: Timing Conditions Symbol Parameter Min Max Unit Figure(s) tCYCLE CTM and CFM cycle times (-800) 2.5 2.56 ns Figure 53 tCR, tCF CTM and CFM input rise and fall times 0.2 0.5 ns Figure 53 tCH, tCL CTM and CFM high and low times 40% 60% tCYCLE Figure 53 tTR CTM-CFM differential (MSE/MS=0/0) 0.0 0.5 tCYCLE Figure 42 tDCW Domain crossing window -0.1 0.1 tCYCLE Figure 59 tDR, tDF DQA/DQB/ROW/COL input rise/fall times 0.2 0.65 ns Figure 54 tS, tH DQA/DQB/ROW/COL-to-CFM setup/hold @ tCYCLE=2.5ns 0.250 0.250 ns Figure 54 tDR1, tDF1 SIO0, SIO1 input rise and fall times - 5.0 ns Figure 56 tDR2, tDF2 CMD, SCK input rise and fall times - 2.0 ns Figure 56 |
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