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KM416RD8AS-RBM80 Datasheet(PDF) 56 Page - Samsung semiconductor |
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KM416RD8AS-RBM80 Datasheet(HTML) 56 Page - Samsung semiconductor |
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56 / 64 page ![]() Page 53 KM416RD8AS Direct RDRAM™ Rev. 0.9 July 1999 Target Figure 58 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The tPROP1 parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1 inputs must be tDR1 and tDF1, measured at the 20% and 80% levels. The rise and fall times of SIO0 and SIO1 outputs are tQR1 and tQF1, measured at the 20% and 80% levels. RSL - Domain Crossing Window When read data is returned by the RDRAM, imformation must cross from the receive clock domain (CFM) to the transmit clock domain (CTM). The tTR parameter permits the CFM to CTM phase to vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. A second parameter tDCW is needed in order to describe how the delay between a RD command packet and read data packet varies as a function of the tTR value. Figure 59 shows this timing for five distinct values of tTR. Case A (tTR=0) is what has been used throughout this docu- ment. The delay between the RD command and read data is tCAC. As tTR varies from zero to tCYCLE (cases A through E), the command to data delay is (tCAC-tTR). When the tTR value is in the range 0 to tDCW,MAX, the command to data delay can also be (tCAC-tTR-tCYCLE). This is shown as cases A’ and B’ (the gray packets). Similarly, when the t TR value is in the range (tCYCLE+tDCW,MIN) to tCYCLE, the command to data delay can also be (tCAC-tTR+tCYCLE). This is shown as cases D’ and E’ (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The delay value is selected at initialization, and remains fixed thereafter. Figure 59: RSL Transmit - Crossing Read Domains CFM COL tTR CTM DQA/B DQA/B tTR=0 tCYCLE Case A tTR=0 Case A’ tTR CTM DQA/B DQA/B tTR=tDCW,MAX Case B tTR=tDCW,MAX Case B’ tTR CTM DQA/B tTR=0.5•t CYCLE Case C CTM DQA/B DQA/B tTR=tCYCLE+tDCW,MIN Case D tTR=tCYCLE+tDCW,MIN Case D’ CTM DQA/B DQA/B tTR=tCYCLE Case E tTR=tCYCLE Case E’ tTR tTR RD a1 Q(a1) Q(a1) Q(a1) Q(a1) tCAC-tTR tCAC-tTR-tCYCLE Q(a1) Q(a1) Q(a1) Q(a1) Q(a1) tCAC-tTR tCAC-tTR+tCYCLE tCAC-tTR tCAC-tTR+tCYCLE tCAC-tTR tCAC -tTR-tCYCLE tCAC-tTR ••• ••• ••• ••• ••• ••• |
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