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KM416RD8AS-RBM80 Datasheet(PDF) 15 Page - Samsung semiconductor

Part # KM416RD8AS-RBM80
Description  128Mbit RDRAM 256K x 16 bit x 2*16 Dependent Banks Direct RDRAMTM for Consumer Package
PDF  64 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

KM416RD8AS-RBM80 Datasheet(HTML) 15 Page - Samsung semiconductor

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Page 12
KM416RD8AS
Direct RDRAM™
Rev. 0.9 July 1999
Target
ROW-to-ROW Packet Interaction
Figure 6 shows two packets on the ROW pins separated by
an interval tRRDELAY which depends upon the packet
contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
noted otherwise. Table 10 summarizes the tRRDELAY values
for all possible cases.
Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
tRR restriction applies to the same device with non-adjacent
banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, tRRDELAY is tRC (tRAS to the PRER command,
and tRP to the next ACT).
Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
RR8, the tRAS restriction means the activated bank must wait
before it can be precharged.
Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba+-1) is precharged or activated. In cases RR11 and
RR12, the same and adjacent banks must all wait tRP for the
sense amp and bank to precharge before being activated.
Figure 6: ROW-to-ROW Packet Interaction- Timing
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T0
T4
T8
T12
T1
T5
T9
T13
T2
T6
T10
T14
T3
T7
T11
T15 T16
T
T17 T18 T19
Transaction a: ROPa
Transaction b: ROPb
a0 = {Da,Ba,Ra}
b0= {Db,Bb,Rb}
tRRDELAY
ROPa a0
ROPb b0
Table 10: ROW-to-ROW Packet Interaction - Rules
Case #
ROPa
Da
Ba
Ra
ROPb
Db
Bb
Rb
tRRDELAY
Example
RR1
ACT
Da
Ba
Ra
ACT
/= Da
xxxx
x..x
tPACKET
Figure 11
RR2
ACT
Da
Ba
Ra
ACT
== Da
/= {Ba,Ba+1,Ba-1}
x..x
tRR
Figure 11
RR3
ACT
Da
Ba
Ra
ACT
== Da
== {Ba+1,Ba-1}
x..x
tRC - illegal unless PRER to Ba/Ba+1/Ba-1
Figure 10
RR4
ACT
Da
Ba
Ra
ACT
== Da
== {Ba}
x..x
tRC - illegal unless PRER to Ba/Ba+1/Ba-1
Figure 10
RR5
ACT
Da
Ba
Ra
PRER
/= Da
xxxx
x..x
tPACKET
Figure 11
RR6
ACT
Da
Ba
Ra
PRER
== Da
/= {Ba,Ba+1,Ba-1}
x..x
tPACKET
Figure 11
RR7
ACT
Da
Ba
Ra
PRER
== Da
== { Ba+1,Ba-1}
x..x
tRAS
Figure 10
RR8
ACT
Da
Ba
Ra
PRER
== Da
== {Ba}
x..x
tRAS
Figure 15
RR9
PRER
Da
Ba
Ra
ACT
/= Da
xxxx
x..x
tPACKET
Figure 12
RR10
PRER
Da
Ba
Ra
ACT
== Da
/= {Ba,Ba+-1,Ba+-2}
x..x
tPACKET
Figure 12
RR10a
PRER
Da
Ba
Ra
ACT
== Da
== {Ba+2}
x..x
tPACKET/tRP if Ba+1 is precharged/activated.
RR10b
PRER
Da
Ba
Ra
ACT
== Da
== {Ba-2}
x..x
tPACKET/tRP if Ba-1 is precharged/activated.
RR11
PRER
Da
Ba
Ra
ACT
== Da
== {Ba+1,Ba-1}
x..x
tRP
Figure 10
RR12
PRER
Da
Ba
Ra
ACT
== Da
== {Ba}
x..x
tRP
Figure 10
RR13
PRER
Da
Ba
Ra
PRER
/= Da
xxxx
x..x
tPACKET
Figure 12
RR14
PRER
Da
Ba
Ra
PRER
== Da
/= {Ba,Ba+1,Ba-1}
x..x
tPP
Figure 12
RR15
PRER
Da
Ba
Ra
PRER
== Da
== {Ba+1,Ba-1}
x..x
tPP
Figure 12
RR16
PRER
Da
Ba
Ra
PRER
== Da
== Ba
x..x
tPP
Figure 12



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