KM416RD8AS-RBM80 datasheet(45/64 Pages) SAMSUNG

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Page 42

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Refresh

RDRAMs, like any other DRAM technology, use volatile

storage cells which must be periodically refreshed. This is

accomplished with the REFA command. Figure 50 shows an

example of this.

The REFA command in the transaction is typically a broad-

cast command (DR4T and DR4F are both set in the ROWR

packet), so that in all devices bank number Ba is activated

with row number REFR, where REFR is a control register in

the RDRAM. When the command is broadcast and ATTN is

set, the power state of the RDRAMs (ATTN or STBY) will

remain unchanged. The controller increments the bank

address Ba for the next REFA command. When Ba is equal

to its maximum value, the RDRAM automatically incre-

ments REFR for the next REFA command.

On average, these REFA commands are sent once every

tREF/2

BBIT+RBIT (where BBIT are the number of bank

address bits and RBIT are the number of row address bits) so

that each row of each bank is refreshed once every tREF

interval.

The REFA command is equivalent to an ACT command, in

terms of the way that it interacts with other packets (see

Table 10). In the example, an ACT command is sent after

tRR to address b0, a different (non-adjacent) bank than the

REFA command.

A second ACT command can be sent after a time tRC to

address c0, the same bank (or an adjacent bank) as the REFA

command.

Note that a broadcast REFP command is issued a time tRAS

after the initial REFA command in order to precharge the

refreshed bank in all RDRAMs. After a bank is given a

REFA command, no other core operations (activate or

precharge) should be issued to it until it receives a REFP.

It is also possible to interleave refresh transactions (not

shown). In the figure, the ACT b0 command would be

replaced by a REFA b0 command. The b0 address would be

broadcast to all devices, and would be {Broadcast, Ba+2,

REFR}. Note that the bank address should skip by two to

avoid adjacent bank interference. A possible bank incre-

menting pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14,

0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16,

18, 20, 22, 31}. Every time bank 31 is reached, the REFA

command would automatically increment the REFR register.

A second refresh mechanism is available for use in PDN and

NAP power states. This mechanism is called self-refresh

mode. When the PDN power state is entered, or when NAP

power state is entered with the NSR control register bit set,

then self-refresh is automatically started for the RDRAM.

Self-refresh uses an internal time base reference in the

RDRAM. This causes an activate and precharge to be

carried out once in every tREF/2

BBIT+RBIT interval. The

REFB and REFR control registers are used to keep track of

the bank and row being refreshed.

Before a controller places an RDRAM into self-refresh

mode, it should perform REFA/REFP refreshes until the

bank address is equal to the maximum value. This ensures

that no rows are skipped. When a controller returns an

RDRAM to REFA/REFP refresh, it should start with the

minimum bank address value (zero).

Figure 50: REFA/REFP Refresh Transaction Example

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

REFA a0

ACT c0

tRAS

tRC

tRP

Transaction a: REFA

a0 = {Broadcast,Ba,REFR}

a1 = {Broadcast,Ba}

Transaction c: xx

c0 = {Dc, ==Ba, Rc}

REFA d0

tREF/2

BBIT+RBIT

BBIT = # bank address bits

RBIT = # row address bits

ACT b0

Transaction d: REFA

d0 = {Broadcast,Ba+1,REFR}

REFB = REFB3..REFB0

REFR = REFR8..REFR0

tRR

Transaction b: xx

b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}

REFP a1

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