KM416RD8AS-RBM80 datasheet(26/64 Pages) SAMSUNG

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Page 23

KM416RD8AS

Direct RDRAM™

Rev. 0.9 July 1999

Target

Write/Retire Examples - continued

The RD will prevent a retire of the first WR from automati-

cally happening. But the first dualoct D(a1) in the write

buffer will be overwritten by the second WR dualoct D(b1)

if the RD command is issued in the third COLC packet.

Therefore, it is required in this situation that the controller

issue a NOCOP command in the third COLC packet,

delaying the RD command by a time of tPACKET. This situa-

tion is explicitly shown in Table 12 for the cases in which

tCCDELAY is equal to tRTR.

Figure 19 shows a possible result when a retire is held off for

a long time (an extended version of Figure 18-left). After a

WR command, a series of six RD commands are issued to

the same device (but to any combination of bank and column

addresses). In the meantime, the bank Ba to which the WR

command was originally directed is precharged, and a

different row Rc is activated. When the retire is automati-

cally performed, it is made to this new row, since the write

buffer only contains the bank and column address, not the

row address. The controller can insure that this doesn’t

happen by never precharging a bank with an unretired write

buffer. Note that in a system with more than one RDRAM,

there will never be more than two RDRAMs with unretired

write buffers. This is because a WR command issued to one

device automatically retires the write buffers of all other

devices written a time tRTR before or earlier.

Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17

T21

T18

T22

T19

T23

Transaction a: WR

Transaction b: RD

a1= {Da,Ba,Ca1}

b1= {Da,Bb,Cb1}

Transaction a: WR

Transaction b: WR

a1= {Da,Ba,Ca1}

b1= {Da,Bb,Cb1}

D (a1)

WR a1

retire (a1)

MSK (a1)

RD b1

Q (b1)

tCWD

tCAC

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T17 T18 T19

D (a1)

WR a1

RD c1

tRTR

retire (a1)

MSK (a1)

tCWD

tCAC

WR b1

D (b1)

Transaction c: RD

c1= {Da,Bc,Cc1}

The controller must insert a NOCOP to retire (a1)

to make room for the data (b1) in the write buffer

The retire operation for a write can be

held off by a read to the same device

tRTR + tPACKET

Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row

CTM/CFM

DQA7..0

DQB7..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

MSK (a1)

retire (a1)

RD b1

WR a1

PRER a2

tRCD

ACT c0

tRAS

tRC

tRP

ACT a0

tCWD

tRTR

Transaction a: WR

a0 = {Da,Ba,Ra}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba}

RD b2

RD b3

RD b4

RD b5

RD b6

Transaction b: RD

b1 = {Da,Bb,Cb1}

b2 = {Da,Bb,Cb2}

b3= {Da,Bb,Cb3}

b4 = {Da,Bb,Cb4}

b5 = {Da,Bb,Cb5}

b6 = {Da,Bb,Cb6}

Q (b1)

tCAC

Q (b2)

Q (b3)

Q (b4)

Q (b5)

Transaction c: WR

c0 = {Da,Ba,Rc}

D (a1)

The retire operation puts the

write data in the new row

WARNING

This sequence is hazardous

and must be used with caution

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