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PIC18LF4331 Datasheet(PDF) 203 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 203 Page - Microchip Technology |
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203 / 392 page  2010 Microchip Technology Inc. DS39616D-page 203 PIC18F2331/2431/4331/4431 TABLE 18-6: REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 IPR3 — — —PTIP IC3DRIP IC2QEIP IC1IP TMR5IP 56 PIE3 — — —PTIE IC3DRIE IC2QEIE IC1IE TMR5IE 56 PIR3 — — —PTIF IC3DRIF IC2QEIF IC1IF TMR5IF 56 PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 58 PTCON1 PTEN PTDIR — — — — — — 58 PTMRL(1) PWM Time Base Register (lower 8 bits) 58 PTMRH(1) UNUSED PWM Time Base Register (upper 4 bits) 58 PTPERL(1) PWM Time Base Period Register (lower 8 bits) 58 PTPERH(1) UNUSED PWM Time Base Period Register (upper 4 bits) 58 SEVTCMPL(1) PWM Special Event Compare Register (lower 8 bits) 58 SEVTCMPH(1) UNUSED PWM Special Event Compare Register (upper 4 bits) 58 PWMCON0 — PWMEN2 PWMEN1 PWMEN0 PMOD3(2) PMOD2 PMOD1 PMOD0 58 PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR — UDIS OSYNC 58 DTCON DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 58 FLTCONFIG BRFEN FLTBS(2) FLTBMOD(2) FLTBEN(2) FLTCON FLTAS FLTAMOD FLTAEN 58 OVDCOND POVD7(2) POVD6(2) POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 58 OVDCONS POUT7(2) POUT6(2) POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 58 PDC0L(1) PWM Duty Cycle #0L Register (lower 8 bits) 58 PDC0H(1) UNUSED PWM Duty Cycle #0H Register (upper 6 bits) 58 PDC1L(1) PWM Duty Cycle #1L register (lower 8 bits) 58 PDC1H(1) UNUSED PWM Duty Cycle #1H Register (upper 6 bits) 58 PDC2L(1) PWM Duty Cycle #2L Register (lower 8 bits) 58 PDC2H(1) UNUSED PWM Duty Cycle #2H Register (upper 6 bits) 58 PDC3L(1,2) PWM Duty Cycle #3L Register (lower 8 bits) 58 PDC3H(1,2) UNUSED PWM Duty Cycle #3H Register (upper 6 bits) 58 Legend: — = Unimplemented, read as ‘0’. Shaded cells are not used with the power control PWM. Note 1: Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. 2: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. Reset values shown are for PIC18F4331/4431 devices. |
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