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PIC18LF4331 Datasheet(PDF) 264 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 264 Page - Microchip Technology |
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264 / 392 page  PIC18F2331/2431/4331/4431 DS39616D-page 264 2010 Microchip Technology Inc. TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300000h CONFIG1L — — — — — — — — ---- ---- 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 300002h CONFIG2L — — — — BORV1 BORV0 BOREN PWRTEN ---- 1111 300003h CONFIG2H — —WINEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN --11 1111 300004h CONFIG3L — —T1OSCMX HPOL LPOL PWMPIN — — --11 11-- 300005h CONFIG3H MCLRE(1) — —EXCLKMX(1) PWM4MX(1) SSPMX(1) —FLTAMX(1) 1--1 11-1 300006h CONFIG4L DEBUG — — — —LVP —STVREN 1--- -1-1 300007h CONFIG4H — — — — — — — — ---- ---- 300008h CONFIG5L — — — —CP3(1) CP2(1) CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — —WRT3(1) WRT2(1) WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H —EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(2) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx (2) 3FFFFFh DEVID2(2) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0101 Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’. Note 1: Unimplemented in PIC18F2331/4331 devices; maintain this bit set. 2: See Register 23-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed U = Unchanged from programmed state bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6 and port function on RA7 (INTIO1) 1000 = Internal oscillator block, port function on RA6 and port function on RA7 (INTIO2) 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 (ECIO) 0100 = EC oscillator, CLKO function on RA6 (EC) 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator |
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