PIC18LF4331 datasheet(272/392 Pages) MICROCHIP

272 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 272

 2010 Microchip Technology Inc.

U-0

R/P-1

—

EBTR3(1,2,3) EBTR2(1,2,3)

EBTR1(2,3)

EBTR0(2,3)

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

U = Unchanged from programmed state

bit 7-4

Unimplemented:

Read as ‘0’

bit 3

EBTR3:

Table Read Protection bit(1,2,3)

= Block 3 is not protected from table reads executed in other blocks

= Block 3 is protected from table reads executed in other blocks

bit 2

EBTR2:

Table Read Protection bit(1,2,3)

= Block 2 is not protected from table reads executed in other blocks

= Block 2 is protected from table reads executed in other blocks

bit 1

EBTR1:

Table Read Protection bit(2,3)

= Block 1 is not protected from table reads executed in other blocks

= Block 1 is protected from table reads executed in other blocks

bit 0

EBTR0:

Table Read Protection bit(2,3)

= Block 0 is not protected from table reads executed in other blocks

= Block 0 is protected from table reads executed in other blocks

Note 1:

Unimplemented in PIC18F2331/4331 devices; maintain this bit set.

Refer to Figure 23-5 for block boundary addresses.

Enabling the corresponding CPx bit is recommended to protect the block from external read operations.

U-0

R/P-1

U-0

—

EBTRB(1,2)

—

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

U = Unchanged from programmed state

bit 7

Unimplemented:

Read as ‘0’

bit 6

EBTRB:

Boot Block Table Read Protection bit(1,2)

= Boot block is not protected from table reads executed in other blocks

= Boot block is protected from table reads executed in other blocks

bit 5-0

Unimplemented:

Read as ‘0’

Note 1:

Enabling the corresponding CPx bit is recommended to protect the block from external read operations.

Refer to Figure 23-5 for block boundary addresses.

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