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PIC18LF4331 Datasheet(PDF) 139 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 139 Page - Microchip Technology |
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139 / 392 page ![]() 2010 Microchip Technology Inc. DS39616D-page 139 PIC18F2331/2431/4331/4431 15.0 TIMER5 MODULE The Timer5 module implements these features: • 16-bit timer/counter operation • Synchronous and Asynchronous Counter modes • Continuous Count and Single-Shot Operating modes • Four programmable prescaler values (1:1 to 1:8) • Interrupt generated on period match • Special Event Trigger Reset function • Double-buffered registers • Operation during Sleep • CPU wake-up from Sleep • Selectable hardware Reset input with a wake-up feature Timer5 is a general purpose timer/counter that incor- porates additional features for use with the Motion Feedback Module (see Section 17.0 “Motion Feed- back Module” ). It may also be used as a general purpose timer or a Special Event Trigger delay timer. When used as a general purpose timer, it can be configured to generate a delayed Special Event Trigger (e.g., an ADC Special Event Trigger) using a preprogrammed period delay. Timer5 is controlled through the Timer5 Control register (T5CON), shown in Register 15-1. The timer can be enabled or disabled by setting or clearing the control bit TMR5ON (T5CON<0>). A block diagram of Timer5 is shown in Figure 15-1. REGISTER 15-1: T5CON: TIMER5 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T5SEN RESEN(1) T5MOD T5PS1 T5PS0 T5SYNC(2) TMR5CS TMR5ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T5SEN: Timer5 Sleep Enable bit 1 = Timer5 is enabled during Sleep 0 = Timer5 is disabled during Sleep bit 6 RESEN: Special Event Trigger Reset Enable bit(1) 1 = Special Event Trigger Reset is disabled 0 = Special Event Trigger Reset is enabled bit 5 T5MOD: Timer5 Mode bit 1 = Single-Shot mode is enabled 0 = Continuous Count mode is enabled bit 4-3 T5PS<1:0>: Timer5 Input Clock Prescale Select bits 11 = 1:8 10 = 1:4 01 = 1:2 00 = 1:1 bit 2 T5SYNC: Timer5 External Clock Input Synchronization Select bit(2) When TMR5CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR5CS = 0: This bit is ignored. Timer5 uses the internal clock when TMR5CS = 0. bit 1 TMR5CS: Timer5 Clock Source Select bit 1 = External clock from the T5CKI pin 0 = Internal clock (TCY) bit 0 TMR5ON: Timer5 On bit 1 = Timer5 is enabled 0 = Timer5 is disabled Note 1: These bits are not implemented on PIC18F2331/2431 devices and read as ‘0’. 2: For Timer5 to operate during Sleep mode, T5SYNC must be set. |
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