PIC18LF4331 datasheet(141/392 Pages) MICROCHIP

141 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 141

PIC18F2331/2431/4331/4431

In Synchronous Counter mode configuration, the timer

is clocked by the external clock (T5CKI) with the

optional prescaler. The external T5CKI is selected by

setting the TMR5CS bit (TMR5CS = 1); the internal

clock is selected by clearing TMR5CS. The external

clock is synchronized to the internal clock by clearing

the T5SYNC bit. The input on T5CKI is sampled on

every Q2 and Q4 of the internal clock. The low to rise

transition is decoded on three adjacent samples and

the Timer5 is incremented on the next Q1. The T5CKI

minimum pulse-width high and low time must be

greater than TCY/2.

In Asynchronous Counter mode configuration, Timer5

is clocked by the external clock (T5CKI) with the

optional prescaler. In this mode, T5CKI is not synchro-

nized to the internal clock. By setting TMR5CS, the

external input clock (T5CKI) can be used as the coun-

ter sampling clock. When T5SYNC is set, the external

clock is not synchronized to the internal device clock.

The timer count is not reset automatically when the

module is disabled. The user may write the Counter

15.1.1

CONTINUOUS COUNT AND

SINGLE-SHOT OPERATION

Timer5 has two operating modes: Continuous Count

and Single-Shot.

Continuous Count mode is selected by clearing the

T5MOD control bit (= 0). In this mode, the Timer5 time

base will start incrementing according to the prescaler

settings until a TMR5/PR5 match occurs, or until TMR5

rolls over (FFFFh to 0000h). The TMR5IF interrupt flag

is set, the TMR5 register is reset on the following input

clock edge and the timer continues to count for as long

as the TMR5ON bit remains set.

Single-Shot mode is selected by setting T5MOD (= 1).

In this mode, the Timer5 time base begins to increment

according to the prescaler settings until a TMR5/PR5

match occurs. This causes the TMR5IF interrupt flag to

be set, the TMR5 register pair to be cleared on the

following input clock edge and the TMR5ON bit to be

cleared by the hardware to halt the timer.

The Timer5 time base can only start incrementing in

Single-Shot mode under two conditions:

Timer5 is enabled (TMR5ON is set), or

Timer5 is disabled and a Special Event Trigger

Reset is present on the Timer5 Reset input. (See

Section 15.7 “Timer5 Special Event Trigger

Reset Input”

for additional information.)

15.2

16-Bit Read/Write and Write Modes

As noted, the actual high byte of the Timer5 register

pair is mapped to TMR5H, which serves as a buffer.

Reading TMR5L will load the contents of the high byte

of the register pair into the TMR5H register. This allows

the user to accurately read all 16 bits of the register pair

without having to determine whether a read of the high

byte, followed by the low byte, is valid due to a rollover

between reads.

Since the actual high byte of the Timer5 register pair is

not directly readable or writable, it must be read and

written to through the Timer5 High Byte Buffer register

(TMR5H). The T5 high byte is updated with the con-

tents of TMR5H when a write occurs to TMR5L. This

allows a user to write all 16 bits to both the high and low

bytes of Timer5 at once. Writes to TMR5H do not clear

the Timer5 prescaler. The prescaler is only cleared on

writes to TMR5L.

15.2.1

16-BIT READ-MODIFY-WRITE

Read-modify-write instructions, like BSF and BCF, will

read the contents of a register, make the appropriate

changes and place the result back into the register. The

write portion of a read-modify-write instruction of

TMR5H will not update the contents of the high byte of

TMR5 until a write of TMR5L takes place. Only then will

the contents of TMR5H be placed into the high byte of

TMR5.

15.3

Timer5 Prescaler

The Timer5 clock input (either TCY or the external clock)

may be divided by using the Timer5 programmable

prescaler. The prescaler control bits, T5PS<1:0>

(T5CON<4:3>), select a prescale factor of 2, 4, 8 or no

prescale.

The Timer5 prescaler is cleared by any of the following:

• A write to the Timer5 register

• Disabling Timer5 (TMR5ON = 0)

• A device Reset such as Master Clear, POR or

BOR

Note:

The Timer5 module does NOT prevent

writes to the PR5 registers (PR5H:PR5L)

while the timer is enabled. Writing to PR5

while the timer is enabled may result in

unexpected period match events.

Note:

Writing to the T5CON register does not

clear the Timer5.

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