PIC18LF4331 datasheet(162/392 Pages) MICROCHIP

162 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 162

 2010 Microchip Technology Inc.

17.2.1

QEI CONFIGURATION

The QEI module shares its input pins with the Input

Capture (IC) module. The inputs are mutually

exclusive; only the IC module or the QEI module (but

not both) can be enabled at one time. Also, because

the IC and QEI are multiplexed to the same input pins,

the programmable noise filters can be dedicated to one

module only.

The operation of the QEI is controlled by the QEICON

Configuration register (see Register 17-2).

Note:

In the event that both QEI and IC are

enabled, QEI will take precedence and IC

will remain disabled.

QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER

R/W-0

R-0

R/W-0

VELM

QERR(1)

UP/DOWN

QEIM2(2,3)

QEIM1(2,3)

QEIM0(2,3)

PDEC1

PDEC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

VELM:

Velocity Mode bit

= Velocity mode disabled

= Velocity mode enabled

bit 6

QERR:

QEI Error bit(1)

= Position counter overflow or underflow(4)

= No overflow or underflow

bit 5

UP/DOWN:

Direction of Rotation Status bit

=Forward

= Reverse

bit 4-2

QEIM<2:0>:

QEI Mode bits(2,3)

111

= Unused

110

= QEI enabled in 4x Update mode; position counter is reset on period match (POSCNT = MAXCNT)

101

= QEI enabled in 4x Update mode; INDX resets the position counter

100

= Unused

010

= QEI enabled in 2x Update mode; position counter is reset on period match (POSCNT = MAXCNT)

001

= QEI enabled in 2x Update mode; INDX resets the position counter

000

= QEI off

bit 1-0

PDEC<1:0>:

Velocity Pulse Reduction Ratio bits

= 1:64

= 1:16

= 1:4

= 1:1

Note 1:

QEI must be enabled and in Index mode.

QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and IC modules

are both enabled, QEI will take precedence.

Enabling one of the QEI operating modes remaps the IC Buffer registers, CAP1BUFH, CAP1BUFL,

CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL, as the VELRH, VELRL, POSCNTH, POSCNTL,

MAXCNTH and MAXCNTL registers (respectively) for the QEI.

The QERR bit must be cleared in software.

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