PIC18LF4331 datasheet(167/392 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39616D-page 167

PIC18F2331/2431/4331/4431

17.2.6

VELOCITY MEASUREMENT

The velocity pulse generator, in conjunction with the

IC1 and the synchronous TMR5 (in synchronous

operation), provides a method for high accuracy speed

measurements at both low and high mechanical motor

speeds. The Velocity mode is enabled when the VELM

bit is cleared (= 0) and QEI is set to one of its operating

modes (see Table 17-6).

To optimize register space, the Input Capture

Channel 1 (IC1) is used to capture TMR5 counter

values. Input Capture Buffer register, CAP1BUF, is

redefined in Velocity Measurement mode, VELM = 0,

as the Velocity Register Buffer (VELRH, VELRL).

TABLE 17-6:

VELOCITY PULSES

17.2.6.1

Velocity Event Timing

The event pulses are reduced by a fixed ratio by the

velocity pulse divider. The divider is useful for

high-speed measurements where the velocity events

happen frequently. By producing a single output pulse

for a given number of input event pulses, the counter

can track larger pulse counts (i.e., distance travelled)

for a given time interval. Time is measured by utilizing

the TMR5 time base.

Each velocity pulse serves as a capture pulse. With the

TMR5 in Synchronous Timer mode, the value of TMR5

is captured on every output pulse of the postscaler. The

counter is subsequently reset to ‘0’. TMR5 is reset

upon a capture event.

Figure 17-13 shows the velocity measurement timing

diagram.

FIGURE 17-12:

VELOCITY MEASUREMENT BLOCK DIAGRAM

QEIM<2:0>

Velocity Event Mode

001

010

x2 Velocity Event mode. The velocity

pulse is generated on every QEA edge.

101

110

x4 Velocity Event mode. The velocity

pulse is generated on every QEA and

QEB active edge.

CAP2/QEA

CAP1/INDX

CAP3/QEB

QEI

Control

Logic

QEB

QEA

INDX

Postscaler

Clock

Direction

Position

Counter

TMR5

IC1

Reset

Logic

Velocity Mode

(VELR Register)

TCY

Clock

TMR5 Reset

Velocity Capture

Velocity Event

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