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ADIS16488 Datasheet(PDF) 13 Page - Analog Devices |
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ADIS16488 Datasheet(HTML) 13 Page - Analog Devices |
13 / 36 page Data Sheet ADIS16488 Rev. B | Page 13 of 36 Name R/W Flash PAGE_ID Address Default Register Description Format XA_ALM_MAGN R/W Yes 0x03 0x2E 0x0000 Alarm, x-axis accelerometer threshold Table 103 YA_ALM_MAGN R/W Yes 0x03 0x30 0x0000 Alarm, y-axis accelerometer threshold Table 104 ZA_ALM_MAGN R/W Yes 0x03 0x32 0x0000 Alarm, z-axis accelerometer threshold Table 105 XM_ALM_MAGN R/W Yes 0x03 0x34 0x0000 Alarm, x-axis magnetometer threshold Table 106 YM_ALM_MAGN R/W Yes 0x03 0x36 0x0000 Alarm, y-axis magnetometer threshold Table 107 ZM_ALM_MAGN R/W Yes 0x03 0x38 0x0000 Alarm, z-axis magnetometer threshold Table 108 BR_ALM_MAGN R/W Yes 0x03 0x3A 0x0000 Alarm, barometer threshold setting Table 109 Reserved N/A N/A 0x03 0x3C to 0x76 N/A Reserved N/A FIRM_REV R Yes 0x03 0x78 N/A Firmware revision Table 50 FIRM_DM R Yes 0x03 0x7A N/A Firmware programming date: day/month Table 51 FIRM_Y R Yes 0x03 0x7C N/A Firmware programming date: year Table 52 Reserved N/A N/A 0x03 0x7E N/A Reserved N/A Reserved N/A N/A 0x04 0x00 to 0x18 N/A Reserved N/A SERIAL_NUM R Yes 0x04 0x20 N/A Serial number Table 54 Reserved N/A N/A 0x04 0x22 to 0x7F N/A Reserved N/A FIR_COEF_Axxx R/W Yes 0x05 0x00 to 0x7E N/A FIR Filter Bank A, Coefficients 0 through 59 Table 59 FIR_COEF_Axxx R/W Yes 0x06 0x00 to 0x7E N/A FIR Filter Bank A, Coefficients 60 through 119 Table 59 FIR_COEF_Bxxx R/W Yes 0x07 0x00 to 0x7E N/A FIR Filter Bank B, Coefficients 0 through 59 Table 60 FIR_COEF_Bxxx R/W Yes 0x08 0x00 to 0x7E N/A FIR Filter Bank B, Coefficients 60 through 119 Table 60 FIR_COEF_Cxxx R/W Yes 0x09 0x00 to 0x7E N/A FIR Filter Bank C, Coefficients 0 through 59 Table 61 FIR_COEF_Cxxx R/W Yes 0x0A 0x00 to 0x7E N/A FIR Filter Bank C, Coefficients 60 through 119 Table 61 FIR_COEF_Dxxx R/W Yes 0x0B 0x00 to 0x7E N/A FIR Filter Bank D, Coefficients 0 through 59 Table 62 FIR_COEF_Dxxx R/W Yes 0x0C 0x00 to 0x7E N/A FIR Filter Bank D, Coefficients 60 through 119 Table 62 1 The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. |
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