ADS8328IBPW datasheet(30/50 Pages) TI

30 / 50 page

ADS8327

ADS8328

SLAS415E

– APRIL 2006 – REVISED JANUARY 2011

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Internal Register

The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration

data register (CFR).

Table 4. Command Set Defined by Command Register (CMR)(1)

WAKE UP FROM

MINIMUM SCLKs

D[15:12]

HEX

COMMAND

D[11:0]

R/W

AUTO NAP

REQUIRED

0000b

Select analog input channel 0(2)

Don't care

0001b

Select analog input channel 1(2)

Don't care

0010b

Reserved

–

0011b

Reserved

–

0100b

Reserved

–

0101b

Reserved

–

0110b

Reserved

–

0111b

Reserved

–

1000b

Reserved

–

1001b

Reserved

–

1010b

Reserved

–

1011b

Wake up

Don't care

1100b

Read CFR

Don't care

–

1101b

Read data

Don't care

–

1110

Write CFR

CFR Value

–

1111b

Default mode (load CFR with default value)

Don't care

(1)

When SDO is not in 3-state (FS/CS low and SCLK running), the bits from SDO are always part (depending on how many SCLKs are

supplied) of the previous conversion result.

(2)

These two commands apply to the ADS8328 only.

WRITING TO THE CONVERTER

There are two different types of writes to the register, a 4-bit write to the CMR and a full 16-bit write to the CMR

plus CFR. The command set is listed in Table 4. A simple command requires only 4 SCLKs and the write takes

effect at the 4th falling edge of SCLK. A 16-bit write or read takes at least 16 SCLKs (see Table 7 for exceptions

that require more than 16 SCLKs).

Configuring the Converter and Default Mode

The converter can be configuring with command 1110b (write to the CFR) or command 1111b (default mode). A

write to the CFR requires a 4-bit command followed by 12-bits of data. A 4-bit command takes effect at the fourth

falling edge of SCLK. A CFR write takes effect at the 16th falling edge of SCLK.

A default mode command can be achieved by simply tying SDI to +VBD. As soon as the chip is selected at least

four 1s are clocked in by SCLK. The default value of the CFR is loaded into the CFR at the 4th falling edge of

SCLK.

CFR default values are all 1s (except for CFR_D1, this bit is ignored by the ADS8327 and is always read as a 0).

The same default values apply for the CFR after a power-on reset (POR) and SW reset.

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