| Electronic Components Datasheet Search |
|
ADS8328IBPW Datasheet(PDF) 11 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADS8328IBPW Datasheet(HTML) 11 Page - Texas Instruments |
|
11 / 50 page ![]() ADS8327 ADS8328 www.ti.com SLAS415E – APRIL 2006 – REVISED JANUARY 2011 ADS8327 Terminal Functions NO. NAME I/O DESCRIPTION TSSOP QFN AGND 5 15 – Analog ground BDGND 14 8 – Interface ground CONVST 9 3 I Freezes sample and hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed EOC/ INT/ CDI 10 4 O duration after the end of conversion and valid data are to be output. The polarity of EOC or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface FS/CS 11 5 slave select (SS –). +IN 3 13 I Noninverting input –IN 4 14 I Inverting input, usually connected to ground NC 8 2 No connection REF+ 7 1 I External reference input. REF – 6 16 I Connect to AGND through individual via. RESERVED 2 12 – Reserved, connect to AGND or +VA SCLK 15 9 I Clock for serial interface SDI 12 6 I Serial data in SDO 13 7 O Serial data out +VA 1 11 Analog supply, +2.7 V to +5.5 VDC. +VBD 16 10 Interface supply ADS8328 Terminal Functions NO. NAME I/O DESCRIPTION TSSOP QFN AGND 5 15 – Analog ground BDGND 14 8 – Interface ground COM 4 14 I Common inverting input, usually connected to ground CONVST 9 3 I Freezes sample and hold, starts conversion with next rising edge of internal clock Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress. If programmed as an interrupt (INT), this pin is low for a preprogrammed EOC/ INT/ 10 4 O duration after the end of conversion and valid data are to be output. The polarity of EOC CDI or INT is programmable. This pin can also be used as a chain data input when the device is operated in chain mode. FS/CS 11 5 I Frame sync signal for TMS320 DSP serial interface or chip select input for SPI interface +IN1 2 12 I Second noninverting input. +IN0 3 13 I First noninverting input NC 8 2 – No connection. REF+ 7 1 I External reference input. REF – 6 16 I Connect to AGND through individual via. SCLK 15 9 I Clock for serial interface SDI 12 6 I Serial data in (conversion start and reset possible) SDO 13 7 O Serial data out +VA 1 11 Analog supply, +2.7 V to +5.5 VDC. +VBD 16 10 Interface supply © 2006–2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS8327 ADS8328 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |