ADS8328IBPW datasheet(32/50 Pages) TI

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ADS8327

SDI

SDO

ADS8327

SDI

SDO

ADS8327

SDI

SDO

MicroController

SDI

SDO

GPIO1

GPIO2

GPIO3

ProgramDevice#1CFR_D5=1

INT

CONVST

EOC/INT

CDI

ProgramDevices#2and#3CFR_D5=0

SCLK

ADS8327

ADS8328

SLAS415E

– APRIL 2006 – REVISED JANUARY 2011

www.ti.com

NOTE

Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion of

the conversion result is output at the SDO pin. The number of bits depends on how many

SCLKs are supplied. For example, a manual select channel command cycle requires 4

SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The exception is

SDO outputs all 1s during the cycle immediately after any reset (POR or software reset).

If SCLK is used as the conversion clock (CCLK) and a continuous SCLK is used, it is not possible to clock out all

16 SDO bits during the sampling time (6 SCLKs) because of the quiet zone requirement. In this case it is better

to read the conversion result during the conversion time (36 SCLKs or 48 SCLKs in auto nap mode).

Table 6. Ideal Input Voltages and Output Codes

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT

Full scale range

VREF

STRAIGHT BINARY

Least significant bit (LSB)

VREF/65536

BINARY CODE

HEX CODE

Full scale

+VREF – 1 LSB

1111 1111 1111 1111

FFFF

Midscale

VREF/2

1000 0000 0000 0000

8000

Midscale

– 1 LSB

VREF/2– 1 LSB

0111 1111 1111 1111

7FFF

Zero

0 V

0000 0000 0000 0000

0000

TAG Mode

The ADS8328 includes a feature, TAG, that can be used as a tag to indicate which channel sourced the

converted result. An address bit is added after the LSB read out from SDO indicating which channel the result

came from if TAG mode is enabled. This address bit is 0 for channel 0 and 1 for channel 1. The converter

requires more than the 16 SCLKs that are required for a 4 bit command plus 12 bit CFR or 16 data bits because

of the additional TAG bit.

Chain Mode

The ADS8327/28 can operate as a single converter or in a system with multiple converters. System designers

can take advantage of the simple high-speed SPI compatible serial interface by cascading them in a single chain

when multiple converters are used. A bit in the CFR is used to reconfigure the EOC/INT status pin as a

secondary serial data input, chain data input (CDI), for the conversion result from an upstream converter. This is

chain mode operation. A typical connection of three converters is shown in Figure 59.

Figure 59. Multiple Converters Connected Using Chain Mode

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ADS8328IBPW Datasheet(PDF) 32 Page - Texas Instruments

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