ADS8328IBPW datasheet(29/50 Pages) TI

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ADS8327

ADS8328

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SLAS415E

– APRIL 2006 – REVISED JANUARY 2011

Total Acquisition + Conversion Cycle Time:

Automatic:

= 21 CCLKs

Manual:

≥ 21 CCLKs

Manual + deep

≥ 4SCLK + 100 ms + 3 CCLK + 18 CCLK +16 SCLK + 1 ms

power-down:

Manual + nap power-down:

≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK

Manual + auto nap

≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use wakeup to resume)

power-down:

Manual + auto nap

≥ 1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK +16 SCLK (use CONVST to resume)

power-down:

DIGITAL INTERFACE

The serial clock is designed to accommodate the latest high-speed processors with an SCLK frequency up to 50

MHz. Each cycle is started with the falling edge of FS/CS. The internal data register content which is made

available to the output register at the EOC is presented on the SDO output pin at the falling edge of FS/CS. This

is the MSB. Output data are valid at the falling edge of SCLK with td(SCLKF–SDOVALID) delay so that the host

processor can read it at the falling edge. Serial data input is also read with the falling edge of SCLK.

The complete serial I/O cycle starts with the first falling edge of SCLK after the falling edge of FS/CS and ends

16 (see NOTE) falling edges of SCLK later. The serial interface is very flexible. It works with CPOL = 0, CPHA =

1 or CPOL = 1, CPHA = 0. This means the falling edge of FS/CS may fall while SCLK is high. The same

relaxation applies to the rising edge of FS/CS where SCLK may be high or low as long as the last SCLK falling

edge happens before the rising edge of FS/CS.

NOTE

There are cases where a cycle is four SCLKs or up to 24 SCLKs depending on the read

mode combination. See Table 4 for details.

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ADS8328IBPW Datasheet(PDF) 29 Page - Texas Instruments