ADS8328IBPW datasheet(33/50 Pages) TI

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CONVST #1,

CONVST

#2,

EOC#1

(activelow)

INT #3

(active low)

CS/FS#2,

/FS#3

SCLK#1,

SCLK#2,

SCLK#3

SDO#1,

CDI#2

SDO#2,

CDI#3

SDO#3

SDI#1,

SDI#2,

SDI#3

CONFIGURE

READResult

Nth

Nthfrom#1

Nthfrom#2

Nthfrom#3

Nthfrom#2

Nthfrom#1

1110............

1101b

1 ..................16

Cascaded ManualTrigger/ReadWhileSampling

(Use internalCCLK,EOCactivelow,and

activelow)held

INT

low duringtheNtimes16bitstransfercycle.

Hi-Z

1 ..................16

1..................16

Hi-Z

CS/FS#1

CONV =18CCLKs

d(SDO-CDI)

SAMPLE1 =3CCLKsmin

d(CSR-EOS) =20nsmin

d(SDO-CDI)

ADS8327

ADS8328

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SLAS415E

– APRIL 2006 – REVISED JANUARY 2011

When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest

of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the

CDI input data goes straight to the output register, therefore the serial input data passes through the converter

with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active. See Figure 60 for

detailed timing. In this timing the conversion in each converters are done simultaneously.

Figure 60. Simplified Cascade Mode Timing with Shared CONVST and Continuous CS

Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The

different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).

The first 16-bit word after the falling chip select is always the data from the chip that received the chip select

signal.

Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and so

on. This is shown in Figure 60. If there is no upstream converter in the chain, as converter #1 in the example, the

same data from the converter is going to be shown repeatedly.

Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in Figure 61, the same

data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired result.

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