ADS8328IBPW datasheet(23/50 Pages) TI

23 / 50 page

ADS8327

+IN

THS4031

20 W

600 W

1VDC

600 W

InputSignal

( 2Vto2V)

+VA

470pF

OSC

Divider

1/2

= 1

= 0

Conversion Clock

(CCLK)

CFR_D10

SPI Serial

Clock (SCLK)

ADS8327

ADS8328

www.ti.com

SLAS415E

– APRIL 2006 – REVISED JANUARY 2011

Figure 53. Bipolar Input Drive Configuration

REFERENCE

The ADS8327/28 can operate with an external reference with a range from 0.3 V to 4.2 V. A clean, low noise,

well-decoupled reference voltage on this pin is required to ensure good performance of the converter. A low

noise band-gap reference like the REF3240 can be used to drive this pin. A 10-mF ceramic decoupling capacitor

is required between the REF+ and REF

– pins of the converter. These capacitors should be placed as close as

possible to the pins of the device. REF

– should be connected to its own via to the analog ground plane with the

shortest possible distance.

CONVERTER OPERATION

The ADS8327/28 has an oscillator that is used as an internal clock which controls the conversion rate. The

frequency of this clock is 10.5 MHz minimum. The oscillator is always on unless the device is in the deep

power-down state or the device is programmed for using SCLK as the conversion clock (CCLK). The minimum

acquisition (sampling) time takes 3 CCLKs (this is equivalent to 238 ns at 12.6 MHz) and the conversion time

takes 18 conversion clocks (CCLK) (~1500 ns) to complete one conversion.

The conversion can also be programmed to run based on the external serial clock, SCLK, if is so desired. This

allows a system designer to achieve system synchronization. The serial clock SCLK, is first reduced to 1/2 of its

frequency before it is used as the conversion clock (CCLK). For example, with a 21-MHz SCLK this provides a

10.5-MHz clock for conversions. If it is desired to start a conversion at a specific rising edge of the SCLK when

the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start of conversion

is selected), the setup time between CONVST and that rising SCLK edge should be observed. This ensures the

conversion is complete in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization

between CONVST and SCLK. In many cases the conversion can start one SCLK period (or CCLK) later which

results in a 19 CCLK (or 37 SCLK) conversion. The 20 ns setup time is not required once synchronization is

relaxed.

The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirements of 8 ns.

Since the ADS8327/28 is designed for high-speed applications, a higher serial clock (SCLK) must be supplied to

be able to sustain the high throughput with the serial interface and so the clock period of SCLK must be at most

1 ms (when used as conversion clock (CCLK). The minimum clock frequency is also governed by the parasitic

leakage of the capacitive digital-to-analog (CDAC) capacitors internal to the ADS8327/28.

Figure 54. Converter Clock

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ADS8328IBPW Datasheet(PDF) 23 Page - Texas Instruments

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