ADS8328IBPW datasheet(21/50 Pages) TI

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ADS8327

ADS8328

www.ti.com

SLAS415E

– APRIL 2006 – REVISED JANUARY 2011

TYPICAL CHARACTERISTICS (continued)

FFT

Figure 49.

Figure 50.

THEORY OF OPERATION

The ADS8327/28 is a high-speed, low power, successive approximation register (SAR) analog-to-digital

converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which

inherently includes a sample/hold function.

The ADS8327/28 has an internal clock that is used to run the conversion but can also be programmed to run the

conversion based on the external serial clock, SCLK.

The ADS8327 has one analog input. The analog input is provided to two input pins: +IN and

–IN. When a

conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a

conversion is in progress, both +IN and

–IN inputs are disconnected from any internal function.

The ADS8328 has two inputs. Both inputs share the same common pin

—COM. The negative input is the same

as the

–IN pin for the ADS8327. The ADS8328 can be programmed to select a channel manually or can be

programmed into the auto channel select mode to sweep between channel 0 and 1 automatically.

ANALOG INPUT

When the converter enters hold mode, the voltage difference between the +IN and

–IN inputs is captured on the

internal capacitor array. The voltage on the

–IN input is limited between AGND – 0.2 V and AGND + 0.2 V,

allowing the input to reject small signals which are common to both the +IN and

–IN inputs. The +IN input has a

range of

–0.2 V to VREF + 0.2 V. The input span (+IN – (–IN)) is limited to 0 V to VREF.

The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input

voltage, and source impedance. The current into the ADS8327/28 charges the internal capacitor array during the

sample period. After this capacitance has been fully charged, there is no further input current. The source of the

analog input voltage must be able to charge the input capacitance (45 pF) to a 16-bit settling level within the

minimum acquisition time (238 ns). When the converter goes into hold mode, the input impedance is greater than

1 G

Ω.

Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN

and

–IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges,

converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass

filters should be used. Care should be taken to ensure that the output impedance of the sources driving the +IN

and

–IN inputs are matched. If this is not observed, the two inputs could have different settling times. This may

result in an offset error, gain error, and linearity error which change with temperature and input voltage.

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