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UPD30121 Datasheet(PDF) 51 Page - NEC

Part # UPD30121
Description  VR4121TM 64-/32-BIT MICROPROCESSOR
PDF  76 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD30121 Datasheet(HTML) 51 Page - NEC

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Data Sheet U14691EJ1V0DS00
51
µµµµPD30121
(12) System bus parameter (IOCHRDY) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
tBCLKH1
Note 1
45
ns
BUSCLK high-level width
tBCLKH2
Note 2
10
ns
tBCLKL1
Note 1
45
ns
BUSCLK low-level width
tBCLKL2
Note 2
10
ns
Address setup time (to BUSCLK)
tAVCK
15
ns
Address setup time (to command signal
↓)
Notes 3, 4
tAVCL
T
× N − 29
ns
Command signal setup time (to BUSCLK)
Note 3
tCLCK
15
ns
Command signal low-level width
Notes 3, 4
tCLCH
2
× T × N − 29
ns
Address hold time (from command signal
↑)
Note 3
tCHAV
25
ns
Command signal recovery time
Notes 3, 4
tCHCL
T
× (N + 1) − 29
ns
IOCHRDY sampling time
Note 4
tCLR
0T
× N − 44
ns
Command signal
↑ delay time from IOCHRDY ↑
Notes 3, 4
tRHCH
T
× N2 × T × N + 29
ns
IOCHRDY hold time (from command signal
↑)
Note 3
tCHRL
0ns
Data output setup time (to command signal
↓)
Note 3
tDVCL
0ns
Data output hold time (from command signal
↑)
Note 3
tCHDV
25
ns
MEMCS16#/IOCS16# sampling start time
Note 4
tAVSV1
2
× T × N − 44
ns
MEMCS16#/IOCS16# hold time (from command
signal
↓)
Note 3
tCHSV
0ns
Data input setup time
tDS
0ns
Data input hold time
tDH
5ns
Notes 1. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 0.
2. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 1.
3. With the VR4121, the MEMW#, MEMR#, IOW#, and IOR# signals are called the command signals for
the system bus interface.
4. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register.
The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and
DTR#/CLKSEL0 pins).
CLKSEL2
Signal
CLKSEL1
Signal
CLKSEL0
Signal
T (ns)
WISAA2 Bit
WISAA1 Bit
WISAA0 Bit
N (TClock)
111
RFU
0
008
110
35
0
017
101
33
0
106
100
30
0
115
011
33
1
Note
0
Note
0
Note
4
010
30
1
Note
0
Note
1
Note
3
001
33
1
1
0
000
38
1
1
1
Remarks 1. Do not set CLKSEL (2:0) signal
= 111.
2. Do not set CLKSEL (2:0) signal
= 110, 101 with 131 MHz model.
Note If the WISAA (0:2) bits are set to 100 or
high when BSEL bit of BCUCNTREG3
register is 0, the AC characteristics of tAVCK
and tCLCK are not guaranteed.



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