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UPD30121 Datasheet(PDF) 6 Page - NEC |
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UPD30121 Datasheet(HTML) 6 Page - NEC |
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6 / 76 page  Data Sheet U14691EJ1V0DS00 6 µµµµPD30121 INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS LCD panel 480 × 240 PD16661 µ PC card PCMCIA /buffer ROM/SROM/flash memory EDO DRAM/ SDRAM OSB OSB PLL HSP RTC DSU ICU PMU DCU CMU DMAAU CODEC AFE VR4120 CPU core 131/168 MHz BCU 32.768 kHz 18.432 MHz VR4121 LCD module GIU KIU AIU LED D/A PIU A/D SIU FIR RS-232C driver IR driver Touch panel 48 MHz CPU CORE INTERNAL BLOCK DIAGRAM Virtual address bus Internal data bus Control (o) Control (i) Address/data (o) Address/data (i) Bus interface Data cache (8 Kbytes) Instruction cache (16 Kbytes) TLB CP0 CPU Clock generator Internal clock |
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