UM0324 datasheet(44/105 Pages) STMICROELECTRONICS

44 / 105 page

Library functions

UM0324

44/105

Fortunately, as discussed in Section 4.2.4,to reconstruct the currents flowing through a

generic three-phase load, it is sufficient to simultaneously sample only two out of three

currents, the third one being computed from the relation given in Section 4.2.4. Thus,

depending on the space vector sector, the A/D conversion of voltage V will be performed

only on the two phases where the duty cycles applied to the low side switches are the

highest. In particular, by looking at Figure 20, you can deduct that in sectors 1 and 6, the

voltage on the Phase A shunt resistor can be discarded; likewise, in sectors 2 and 3 for

Phase B, and finally in sectors 4 and 5 for Phase C.

Moreover, in order to properly synchronize the two stator current reading A/D conversions, it

is necessary to distinguish between the different situations that can occur depending on

PWM frequency and applied duty cycles.

Note:

The explanations below refer to space vector sector 1. They can be applied in the same

manner to the other sectors.

Case 1: Duty cycle applied to Phase A low side switch is larger than

DT+TN+ 2TS + TH + TDMA

Where:

●

DT is dead time.

●

TN is the duration of the noise induced on the shunt resistor voltage of a phase by the

commutation of a switch belonging to another phase.

●

TS is the sampling time of the STR750 A/D converter. Refer to the STR750 reference

manual for more detailed information.

●

TH is the holding time of the STR750 A/D converter. Refer to the STR750 reference

manual for more detailed information.

●

TDMA is the time required for the DMA to load the value related to the next conversion

delay in TIM0 OCR2 (refer to Section 4.2.4: Current sampling in three shunt topology

and general purpose A/D conversions on page 41 for further details).

This case typically occurs when SVPWM with low (<60%) modulation index is generated

(see Figure 24). The modulation index is the applied phase voltage magnitude expressed as

a percentage of the maximum applicable phase voltage (the duty cycle ranges from 0% to

100%).

Figure 25 offers a reconstruction of the PWM signals applied to low side switches of Phase

A and B in these conditions plus a view of the analog voltages measured on the STR750

A/D converter pins for both Phase B and C (the time base is lower than the PWM period).

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