PIC18F010 datasheet(45/176 Pages) MICROCHIP

45 / 176 page

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 43

PIC18F010/020

5.0

DATA EEPROM MEMORY

The Data EEPROM is readable and writable during

normal operation (full VDD range). This memory is not

directly mapped in the register file space. Instead, it is

indirectly addressed through the Special Function Reg-

isters. There are four SFRs used to read and write this

memory. These registers are:

• EECON1 (0FA6h)

• EECON2 (0FA7h)

• EEDATA (0FA8h)

• EEADR (0FA9h)

When interfacing the data memory block, EEDATA

holds the 8-bit data for read/write, and EEADR holds

the address of the EEPROM location being accessed.

These devices have 64 bytes of data EEPROM with an

address range from 0h to 03Fh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write).

The EEPROM data memory is rated for high erase/

write cycles. The write time is controlled by an on-chip

timer. The write time will vary with voltage and temper-

ature, as well as from chip-to-chip. Please refer to the

specifications for exact limits.

When the device is code protected, the CPU may con-

tinue to read and write the data EEPROM memory.

5.1

EEADR

The EEADR register can address up to a maximum of

256 bytes of data.

When the device contains less memory than the full

address reach of the EEADR register, the MSb’s of the

64 bytes of data EE, the Most Significant 2 bits of the

5.2

EECON1 and EECON2 Registers

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all '0's. The EECON2 register is used

exclusively in the memory write sequence.

Control bit EEPGD determines if the access will be a

program or a data memory access. When clear, any

subsequent operations will operate on the data mem-

ory. When set, any subsequent operations will operate

on the program memory.

Control bits RD and WR initiate read and write opera-

tions, respectively. These bits cannot be cleared, only

set, in software. They are cleared in hardware at the

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

or premature termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset, during normal oper-

ation. In these situations, following RESET, the user

can check the WRERR bit and rewrite the location. The

value of the data and address registers and the

EEPGD bit remains unchanged.

Interrupt flag bit EEIF in the PIR2 register, is set when

a write is complete. It must be cleared in software.

PIC18F010 Datasheet(PDF) 45 Page - Microchip Technology

PIC18F010 Datasheet(HTML) 45 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL