PIC18F010 datasheet(92/176 Pages) MICROCHIP

92 / 176 page

PIC18F010/020

DS41142A-page 90

Preliminary

 2001 Microchip Technology Inc.

12.3

Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared, but

keeps running, the PD bit (RCON<3>) is cleared, the

TO (RCON<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, and disable

external clocks. Pull all I/O pins that are hi-impedance

inputs, high or low externally, to avoid switching cur-

rents caused by floating inputs. The T0CKI input should

also be at VDD or VSS for lowest current consumption.

The contribution from on-chip pull-ups should be

considered.

The MCLR pin must be at a logic high level (VIHMC), if

enabled.

12.3.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

External RESET input on MCLR pin.

Watchdog

Timer

Wake-up

(if

WDT

was

enabled).

Interrupt from INT pin, RB port change or a

Peripheral Interrupt.

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execution and will cause a "wake-up". The TO and PD

bits in the RCON register can be used to determine the

cause of the device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared, if a WDT time-out occurred (and caused

wake-up).

When the SLEEP instruction is being executed, the next

instruction (PC + 2) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOP after the SLEEP instruction.

PIC18F010 Datasheet(PDF) 92 Page - Microchip Technology

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