PIC18F010 datasheet(46/176 Pages) MICROCHIP

46 / 176 page

PIC18F010/020

DS41142A-page 44

Preliminary

 2001 Microchip Technology Inc.

EECON1 REGISTER (ADDRESS 18Ch)

R/W-U

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

—

FREE

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: FLASH Program or Data EEPROM Memory Select bit

= Access Program FLASH memory

= Access Data EEPROM memory

bit 6-5

Unimplemented: Read as ‘0’

bit 4

FREE: FLASH Row Erase Enable bit

= Erase the row addressed by TBLPTR on the next WR command (reset by hardware)

= Perform write only

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR Reset or any WDT Reset during normal operation)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the EEPROM

bit 1

WR: Write Control bit

= Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR

bit can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD

bit can only be set (not cleared) in software.)

= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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