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PIC18F010 Datasheet(PDF) 20 Page - Microchip Technology |
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PIC18F010 Datasheet(HTML) 20 Page - Microchip Technology |
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20 / 176 page ![]() PIC18F010/020 DS41142A-page 18 Preliminary 2001 Microchip Technology Inc. TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Power-on Reset, Brown-out Reset MCLR Reset WDT Reset Reset Instruction Stack Reset Wake-up via WDT or Interrupt TOSH 0000 0000 0000 0000 uuuu uuuu(3) TOSL 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU ---0 0000 ---0 0000 ---u uuuu PCLATH 0000 0000 0000 0000 uuuu uuuu PCL 0000 0000 0000 0000 PC + 2(2) TBLPTRU ---0 00-- ---0 00-- ---u uu-- TBLPTRH ---- 0000 ---- 0000 ---- uuuu TBLPTRL 0000 0000 0000 0000 uuuu uuuu TABLAT 0000 0000 0000 0000 uuuu uuuu PRODH xxxx xxxx uuuu uuuu uuuu uuuu PRODL xxxx xxxx uuuu uuuu uuuu uuuu INTCON 0000 000x 0000 000u uuuu uuuu(1) INTCON2 11-- -1-1 11-- -1-1 uu-- -u-u(1) INDF0 N/A N/A N/A POSTINC0 N/A N/A N/A POSTDEC0 N/A N/A N/A PREINC0 N/A N/A N/A PLUSW0 N/A N/A N/A FSR0H ---- 0000 ---- 0000 ---- uuuu FSR0L xxxx xxxx uuuu uuuu uuuu uuuu WREG xxxx xxxx uuuu uuuu uuuu uuuu INDF1 N/A N/A N/A POSTINC1 N/A N/A N/A POSTDEC1 N/A N/A N/A PREINC1 N/A N/A N/A PLUSW1 N/A N/A N/A FSR1H ---- 0000 ---- 0000 ---- uuuu FSR1L xxxx xxxx uuuu uuuu uuuu uuuu BSR ---- 0000 ---- 0000 ---- uuuu INDF2 N/A N/A N/A POSTINC2 N/A N/A N/A POSTDEC2 N/A N/A N/A PREINC2 N/A N/A N/A PLUSW2 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard- ware stack. 4: See Table 3-2 for RESET value for specific condition. 5: The long write enable is only reset on a POR or MCLR Reset. |
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