PIC18F010 datasheet(88/176 Pages) MICROCHIP

88 / 176 page

PIC18F010/020

DS41142A-page 86

Preliminary

 2001 Microchip Technology Inc.

CONFIG2H: CONFIGURATION REGISTER 2H (ADDRESS 300003h)

R/P-1

U-0

R/P-1

reserved

—

STVRE

WDTLE

WDPS2

WDPS1

WDPS0

WDTE

bit 7

bit 0

bit 7

Reserved

bit 6

Unimplemented: Read as ’0’

bit 5

STVRE: Stack Full/Underflow Reset Enable bit

= Reset on stack full/underflow enabled

= Disabled

bit 4

WDTLE: Watchdog Timer Long Delay Enable bit

= Use WDPS<2:0> bits to set delay

= Enable long postscaler divider; 16 x WDPS<2:0> bits

bit 3-1

WDPS2:WDPS0: Watchdog Timer Postscale Select bits

111

= 1:128

110

= 1:64

101

= 1:32

100

= 1:16

011

= 1:8

010

= 1:4

001

= 1:2

000

= 1:1

bit 0

WDTE: Watchdog Timer Enable bit

= WDT enabled

= WDT disabled (control is placed on the SWDTE bit)

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

1 = Bit is set

0 = Bit is cleared

x = Bit is unknown

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