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PIC18F010 Datasheet(PDF) 19 Page - Microchip Technology |
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PIC18F010 Datasheet(HTML) 19 Page - Microchip Technology |
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19 / 176 page  2001 Microchip Technology Inc. Preliminary DS41142A-page 17 PIC18F010/020 3.5 Time-out Sequence On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after the POR time delay has expired; then, OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in Internal Oscillator mode with the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5 and Figure 3-6 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18F010/020 device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all the registers. TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS REGISTER 3-1: RCON REGISTER BITS AND POSITIONS TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Oscillator Configuration Power-up(1) Brown-out(1) Wake-up from SLEEP or Oscillator Switch PWRTE = 0 PWRTE = 1 HS, XT, LP 72 ms + 1024Tosc 1024Tosc 72 ms + 1024Tosc 1024Tosc EC 72 ms — 72 ms — External Oscillator 72 ms — 72 ms — Internal Oscillator(2) 72 ms — 72 ms — Note 1: 72 ms is the nominal power-up timer delay. 2: 8-cycle delay. R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-1 R/W-1 IPEN — — RI TO PD POR BOR bit 7 bit 0 Condition Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u MCLR Reset during normal operation 0000h 00-u uuuu u u u u u u u Software Reset during normal operation 0000h 0u-0 uuuu 0 u u u u u u Stack Full Reset during normal operation 0000h 0u-u uu11 u u u u u 1 u Stack Underflow Reset during normal operation 0000h 0u-u uu11 u u u u u u 1 MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u WDT Reset 0000h 0u-u 01uu 1 0 1 u u u u WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u Brown-out Reset 0000h 0u-1 11u0 1 1 1 1 0 u u Interrupt Wake-up from SLEEP PC + 2 ( 1) uu-u 00uu u 1 0 u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). |
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